zephyr/soc/arm/xilinx_zynq7000/xc7zxxx
Henrik Brix Andersen 9d51d9145b soc: arm: xilinx: zynq7000: default to 1 CPU core
Default to 1 CPU core on the Xilinx Zynq-7000 SoC series since Zephyr does
not yet suppport SMP on aarch32.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2022-06-28 20:46:11 +02:00
..
CMakeLists.txt
Kconfig.defconfig.series soc: arm: xilinx: zynq7000: default to 1 CPU core 2022-06-28 20:46:11 +02:00
Kconfig.defconfig.xc7z010
Kconfig.defconfig.xc7z015
Kconfig.defconfig.xc7z020
Kconfig.defconfig.xc7z030
Kconfig.defconfig.xc7z035
Kconfig.defconfig.xc7z045
Kconfig.defconfig.xc7z100
Kconfig.series
Kconfig.soc
linker.ld linker: update files with <zephyr/...> include prefix 2022-05-09 12:45:29 -04:00
soc.c soc: arm: xilinx: zynq7000: unlock the slcr at boot 2022-06-28 20:46:11 +02:00
soc.h