Henrik Brix Andersen 9d51d9145b soc: arm: xilinx: zynq7000: default to 1 CPU core ... Default to 1 CPU core on the Xilinx Zynq-7000 SoC series since Zephyr does not yet suppport SMP on aarch32. Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>		2022-06-28 20:46:11 +02:00
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common	soc: arm: xilinx: zynq7000: add pinctrl header file	2022-06-28 20:46:11 +02:00
xc7zxxx	soc: arm: xilinx: zynq7000: default to 1 CPU core	2022-06-28 20:46:11 +02:00
xc7zxxxs	…
CMakeLists.txt	soc: arm: xilinx: zynq7000: add pinctrl header file	2022-06-28 20:46:11 +02:00
Kconfig	…
Kconfig.defconfig	…
Kconfig.soc	…