56 lines
822 B
Plaintext
56 lines
822 B
Plaintext
/*
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* Copyright (c) 2018 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <mem.h>
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#define DT_DRAM_SIZE DT_SIZE_M(2048)
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#include <intel/apollo_lake.dtsi>
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/ {
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model = "up_squared";
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compatible = "aaeon,up_squared";
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aliases {
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i2c-0 = &i2c0;
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i2c-1 = &i2c1;
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};
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chosen {
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zephyr,sram = &dram0;
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zephyr,console = &uart0;
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zephyr,shell-uart = &uart0;
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zephyr,bt-uart = &uart1;
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zephyr,uart-pipe = &uart1;
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zephyr,bt-mon-uart = &uart1;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "intel,apollo-lake";
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d-cache-line-size = <64>;
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reg = <0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "intel,apollo-lake";
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d-cache-line-size = <64>;
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reg = <1>;
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};
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};
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};
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&hpet {
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status = "disabled";
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};
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