28 lines
435 B
Plaintext
28 lines
435 B
Plaintext
/*
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* Copyright (c) 2018 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <mem.h>
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#define DT_DRAM_SIZE DT_SIZE_M(2048)
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#include <apollo_lake.dtsi>
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/ {
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model = "up_squared";
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compatible = "intel,apollo_lake";
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chosen {
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zephyr,sram = &dram0;
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zephyr,console = &uart0;
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zephyr,shell-uart = &uart0;
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zephyr,bt-uart = &uart1;
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zephyr,uart-pipe = &uart1;
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zephyr,bt-mon-uart = &uart1;
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};
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};
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