4c87224818
This build target has all the low-memory options enabled for memory management: a 4MB address space, 32-bit paging mode, no KPTI, an empty page pool, and common page tables for memory domains. Signed-off-by: Andrew Boie <andrew.p.boie@intel.com> |
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acrn | ||
common/scripts | ||
minnowboard | ||
qemu_x86 | ||
up_squared | ||
index.rst |