190 lines
4.8 KiB
ArmAsm
190 lines
4.8 KiB
ArmAsm
/*
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* Copyright (c) 2014 Wind River Systems, Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* @file
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* @brief Handling of transitions to-and-from regular IRQs (RIRQ)
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*
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* This module implements the code for handling entry to and exit from regular
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* IRQs.
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*
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* See isr_wrapper.S for details.
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*/
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#define _ASMLANGUAGE
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#include <nano_private.h>
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#include <offsets.h>
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#include <toolchain.h>
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#include <arch/cpu.h>
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#include "swap_macros.h"
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GTEXT(_rirq_enter)
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GTEXT(_rirq_exit)
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/**
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*
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* @brief Work to be done before handing control to an IRQ ISR
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*
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* The processor pushes automatically all registers that need to be saved.
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* However, since the processor always runs at kernel privilege there is no
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* automatic switch to the IRQ stack: this must be done in software.
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*
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* Assumption by _isr_demux: r3 is untouched by _rirq_enter.
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*
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* @return N/A
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*/
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SECTION_FUNC(TEXT, _rirq_enter)
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mov r1, _nanokernel
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ld r2, [r1, __tNANO_current_OFFSET]
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#if CONFIG_NUM_REGULAR_IRQ_PRIO_LEVELS == 1
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st sp, [r2, __tTCS_preempReg_OFFSET + __tPreempt_sp_OFFSET]
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ld sp, [r1, __tNANO_rirq_sp_OFFSET]
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#else
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#error regular irq nesting is not implemented
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#endif
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j _isr_demux
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/**
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*
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* @brief Work to be done exiting an IRQ
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*
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* @return N/A
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*/
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SECTION_FUNC(TEXT, _rirq_exit)
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mov r1, _nanokernel
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ld r2, [r1, __tNANO_current_OFFSET]
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#if CONFIG_NUM_REGULAR_IRQ_PRIO_LEVELS > 1
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/* check if we're a nested interrupt: if so, let the interrupted interrupt
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* handle the reschedule */
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lr r3, [_ARC_V2_AUX_IRQ_ACT]
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ffs r0, r3
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asl r0, 1, r0
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/* the OS on ARCv2 always runs in kernel mode, so assume bit31 [U] in
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* AUX_IRQ_ACT is always 0: if the contents of AUX_IRQ_ACT is greater
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* than FFS(AUX_IRQ_ACT), it means that another bit is set so an
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* interrupt was interrupted.
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*/
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cmp r0, r3
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brgt.nd _rirq_return_from_rirq
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ld sp, [r2, __tTCS_preempReg_OFFSET + __tPreempt_sp_OFFSET]
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#endif
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/*
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* Both (a)reschedule and (b)non-reschedule cases need to load the current
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* thread's stack, but don't have to use it until the decision is taken:
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* load the delay slots with the 'load stack pointer' instruction.
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*
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* a) needs to load it to save outgoing context.
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* b) needs to load it to restore the interrupted context.
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*/
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ld r0, [r2, __tTCS_flags_OFFSET]
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and.f r0, r0, PREEMPTIBLE
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bz.d _rirq_no_reschedule
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ld sp, [r2, __tTCS_preempReg_OFFSET + __tPreempt_sp_OFFSET]
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ld r0, [r1, __tNANO_fiber_OFFSET] /* incoming fiber in r0 */
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cmp r0, 0
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bz.d _rirq_no_reschedule
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ld sp, [r2, __tTCS_preempReg_OFFSET + __tPreempt_sp_OFFSET]
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.balign 4
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_rirq_reschedule:
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/* _save_callee_saved_regs expects outgoing thread in r2 */
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_save_callee_saved_regs
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st _CAUSE_RIRQ, [r2, __tTCS_relinquish_cause_OFFSET]
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/* incoming fiber is in r0: it becomes the new 'current' */
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mov r2, r0
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st r2, [r1, __tNANO_current_OFFSET]
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ld r3, [r2, __tTCS_link_OFFSET]
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st r3, [r1, __tNANO_fiber_OFFSET]
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/*
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* _load_callee_saved_regs expects incoming thread in r2.
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* _load_callee_saved_regs restores the stack pointer.
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*/
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_load_callee_saved_regs
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ld r3, [r2, __tTCS_relinquish_cause_OFFSET]
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breq.nd r3, _CAUSE_RIRQ, _rirq_return_from_rirq
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nop
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breq.nd r3, _CAUSE_FIRQ, _rirq_return_from_firq
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nop
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/* fall through */
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.balign 4
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_rirq_return_from_coop:
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/* status32 and pc (blink) are already on the stack in the right order */
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/* update status32.ie (explanation in firq_exit:_firq_return_from_coop) */
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ld r0, [sp, 4]
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ld r3, [r2, __tTCS_intlock_key_OFFSET]
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st 0, [r2, __tTCS_intlock_key_OFFSET]
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cmp r3, 0
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or.ne r0, r0, _ARC_V2_STATUS32_IE
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st r0, [sp, 4]
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/* carve fake stack */
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sub sp, sp, (__tISF_SIZEOF - 12) /* a) status32/pc are already on the stack
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* b) a real value will be pushed in r0 */
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/* push return value on stack */
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ld r0, [r2, __tTCS_return_value_OFFSET]
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push_s r0
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/*
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* r13 is part of both the callee and caller-saved register sets because
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* the processor is only able to save registers in pair in the regular
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* IRQ prologue. r13 thus has to be set to its correct value in the IRQ
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* stack frame.
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*/
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st r13, [sp, __tISF_r13_OFFSET]
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/* stack now has the IRQ stack frame layout, pointing to r0 */
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/* fall through to rtie instruction */
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.balign 4
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_rirq_return_from_firq:
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_rirq_return_from_rirq:
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/* rtie will pop the rest from the stack */
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/* fall through to rtie instruction */
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.balign 4
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_rirq_no_reschedule:
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rtie
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