Jean-Paul Etienne be856d4b13 riscv32: riscv32-qemu: provide a more generic way of filtering IRQs from exceptions ... Currently, if IRQ number != RISCV_MACHINE_TIMER_IRQ (only device IRQ in qemu), riscv32-qemu was considering the IRQ as an exception. However, fake IRQs can also be generated by setting corresponding bits in the Machine Interrupt Pending register (mip). With the current implementation, these IRQs were considered as unexpected exceptions. To circumvent the problem, update the IRQ filtering mechanism by considering an IRQ (IRQ number as reported by the mcause register) as an exception only if its corresponding bit is NOT set in the mip register. Change-Id: I4c581a84d83ee0ba2c4ea35f89ba732401eb8fa4 Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>		2017-02-16 17:33:02 +00:00
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core	riscv32: enable gen_isr_tables mechanism	2017-02-15 04:49:17 +00:00
include	riscv32: move riscv privileged architecture specifics within a common header file	2017-02-14 05:23:14 +00:00
soc	riscv32: riscv32-qemu: provide a more generic way of filtering IRQs from exceptions	2017-02-16 17:33:02 +00:00
Kbuild	…
Kconfig	riscv32: enable gen_isr_tables mechanism	2017-02-15 04:49:17 +00:00
Makefile	riscv32: move riscv privileged architecture specifics within a common header file	2017-02-14 05:23:14 +00:00
defconfig	…