36365e38ba
The code assumes that when the systick counter hits zero, the timer interrupt will be taken before the loop can read the LOAD/VAL registers, but this is not architecturally guaranteed, and so the code can see a post-reload SysTick->VAL and a pre-reload clock_accumulated_count, which causes it to return an incorrectly small cycle count. By adding a ISB we overcome this issue. Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com> |
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| .. | ||
| CMakeLists.txt | ||
| Kconfig | ||
| altera_avalon_timer_hal.c | ||
| arcv2_timer0.c | ||
| cortex_m_systick.c | ||
| hpet.c | ||
| loapic_timer.c | ||
| native_posix_timer.c | ||
| nrf_rtc_timer.c | ||
| pulpino_timer.c | ||
| riscv_machine_timer.c | ||
| sys_clock_init.c | ||
| xtensa_sys_timer.c | ||