78 lines
1.7 KiB
Plaintext
78 lines
1.7 KiB
Plaintext
/*
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* Copyright (c) 2020 Teslabs Engineering S.L.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <st/h7/stm32h7.dtsi>
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/ {
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soc {
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flash-controller@52002000 {
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flash0: flash@8000000 {
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write-block-size = <32>;
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erase-block-size = <DT_SIZE_K(128)>;
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};
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};
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dmamux1: dmamux@40020800 {
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dma-requests= <107>;
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};
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usbotg_fs: usb@40080000 {
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compatible = "st,stm32-otgfs";
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reg = <0x40080000 0x40000>;
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interrupts = <101 0>, <98 0>, <99 0>;
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interrupt-names = "otgfs", "ep1_out", "ep1_in";
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num-bidir-endpoints = <9>;
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ram-size = <4096>;
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maximum-speed = "full-speed";
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x080000000>;
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phys = <&otghs_fs_phy>;
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status = "disabled";
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label= "OTG_FS";
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};
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};
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/* System data RAM accessible over AXI bus: AXI SRAM in D1 domain */
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sram0: memory@24000000 {
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reg = <0x24000000 DT_SIZE_K(512)>;
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compatible = "mmio-sram";
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};
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/* System data RAM accessible over AHB bus: SRAM1 in D2 domain */
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sram1: memory@30000000 {
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reg = <0x30000000 DT_SIZE_K(128)>;
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compatible = "mmio-sram";
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};
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/* System data RAM accessible over AHB bus: SRAM2 in D2 domain */
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sram2: memory@30020000 {
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compatible = "mmio-sram";
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reg = <0x30020000 DT_SIZE_K(128)>;
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};
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/* System data RAM accessible over AHB bus: SRAM3 in D2 domain */
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sram3: memory@30040000 {
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compatible = "mmio-sram";
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reg = <0x30040000 DT_SIZE_K(32)>;
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};
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/* System data RAM accessible over AHB bus: SRAM4 in D3 domain */
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sram4: memory@38000000 {
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reg = <0x38000000 DT_SIZE_K(64)>;
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compatible = "mmio-sram";
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};
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dtcm: memory@20000000 {
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compatible = "arm,dtcm";
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reg = <0x20000000 DT_SIZE_K(128)>;
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};
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otghs_fs_phy: otghs_fs_phy {
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compatible = "usb-nop-xceiv";
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#phy-cells = <0>;
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label = "OTGHS_FS_PHY";
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};
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};
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