816229128d
Fix writing of ICC_SRE_EL3 to or-in bits to align with original intent to read-modify-write this register. Also disable FIQ and IRQ bypass so interrupt delivery occurs through GIC. Platforms may choose to override this behavior in z_arm64_el3_plat_init implementations. Remove ICC_SRE_EL3 config from viper and qemu since this is now handled in the arm64 arch core. Signed-off-by: Eugene Cohen <quic_egmc@quicinc.com> |
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| .. | ||
| CMakeLists.txt | ||
| Kconfig.defconfig.series | ||
| Kconfig.defconfig.viper_bcm58402_a72 | ||
| Kconfig.series | ||
| Kconfig.soc | ||
| linker.ld | ||
| linker_a72.ld | ||
| mmu_regions.c | ||
| plat_core.c | ||
| soc.c | ||
| soc.h | ||