244 lines
7.3 KiB
Plaintext
244 lines
7.3 KiB
Plaintext
# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_ESP32 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3
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config ESP_SPIRAM
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bool "Support for external, SPI-connected RAM"
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default n if MCUBOOT
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help
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This enables support for an external SPI RAM chip, connected in
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parallel with the main SPI flash chip.
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menu "SPI RAM config"
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depends on ESP_SPIRAM
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config ESP_HEAP_MIN_EXTRAM_THRESHOLD
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int "Minimum threshold for external RAM allocation"
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default 8192
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range 1024 131072
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help
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Threshold to decide if memory will be allocated from DRAM
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or SPIRAM. If value of allocation size is less than this value,
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memory will be allocated from internal RAM.
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config ESP_HEAP_SEARCH_ALL_REGIONS
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bool "Search for all available heap regions"
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default y
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help
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This configuration enables searching all available heap
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regions. If the region of desired capability is exhausted,
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memory will be allocated from other available region.
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config ESP_SPIRAM_HEAP_SIZE
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int "Size of SPIRAM heap"
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default 262134 if SYS_HEAP_SMALL_ONLY
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default 1048576 if !SYS_HEAP_SMALL_ONLY
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help
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Specify size of SPIRAM heap.
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choice SPIRAM_MODE
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prompt "Mode (QUAD/OCT) of SPI RAM chip in use"
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default SPIRAM_MODE_QUAD
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config SPIRAM_MODE_QUAD
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bool "Quad Mode PSRAM"
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config SPIRAM_MODE_OCT
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bool "Octal Mode PSRAM"
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depends on SOC_SERIES_ESP32S3
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endchoice # SPIRAM_MODE
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choice SPIRAM_TYPE
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prompt "Type of SPI RAM chip in use"
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default SPIRAM_TYPE_ESPPSRAM16 if SPIRAM_MODE_QUAD
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default SPIRAM_TYPE_ESPPSRAM64
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config SPIRAM_TYPE_ESPPSRAM16
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bool "ESP-PSRAM16 or APS1604"
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depends on SPIRAM_MODE_QUAD
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config SPIRAM_TYPE_ESPPSRAM32
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bool "ESP-PSRAM32 or IS25WP032"
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depends on SPIRAM_MODE_QUAD
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config SPIRAM_TYPE_ESPPSRAM64
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bool "ESP-PSRAM64, LY68L6400 or APS6408"
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endchoice # SPIRAM_TYPE
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config ESP_SPIRAM_SIZE
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int "Size of SPIRAM part"
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default 2097152 if SPIRAM_TYPE_ESPPSRAM16
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default 4194304 if SPIRAM_TYPE_ESPPSRAM32
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default 8388608 if SPIRAM_TYPE_ESPPSRAM64
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help
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Specify size of SPIRAM part.
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NOTE: If SPIRAM size is greater than 4MB, only
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lower 4MB can be allocated using k_malloc().
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choice SPIRAM_SPEED
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prompt "Set RAM clock speed"
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default SPIRAM_SPEED_40M
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help
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Select the speed for the SPI RAM chip.
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config SPIRAM_SPEED_20M
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bool "20MHz clock speed"
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depends on SOC_SERIES_ESP32S2
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config SPIRAM_SPEED_26M
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bool "26MHz clock speed"
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depends on SOC_SERIES_ESP32S2
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config SPIRAM_SPEED_40M
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bool "40MHz clock speed"
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config SPIRAM_SPEED_80M
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bool "80MHz clock speed"
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depends on ESPTOOLPY_FLASHFREQ_80M
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config SPIRAM_SPEED_120M
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bool "120MHz clock speed"
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depends on SPIRAM_MODE_QUAD && SOC_SERIES_ESP32S3
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endchoice # SPIRAM_SPEED
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config SPIRAM_SPEED
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int
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default 120 if SPIRAM_SPEED_120M
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default 80 if SPIRAM_SPEED_80M
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default 40 if SPIRAM_SPEED_40M || SPIRAM_SPEED_26M || SPIRAM_SPEED_20M
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config SPIRAM_CLK_IO
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int
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depends on SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3
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default 30
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config SPIRAM_CS_IO
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int
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depends on SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3
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default 26
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config SPIRAM_FETCH_INSTRUCTIONS
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bool "Move Instructions in Flash to PSRAM"
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depends on SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3
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default n
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help
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If enabled, instructions in flash will be moved into PSRAM on startup.
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If SPIRAM_RODATA is also enabled, code that requires execution during an SPI1 Flash operation
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can forgo being placed in IRAM, thus optimizing RAM usage (see External RAM documentation
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for more details).
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config SPIRAM_RODATA
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bool "Move Read-Only Data in Flash to PSRAM"
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depends on SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3
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default n
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help
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If enabled, rodata in flash will be moved into PSRAM on startup.
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If SPIRAM_FETCH_INSTRUCTIONS is also enabled, code that requires execution during an SPI1 Flash operation
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can forgo being placed in IRAM, thus optimizing RAM usage (see External RAM documentation
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for more details).
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config SPIRAM_ECC_ENABLE
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bool "Allow enabling SPI RAM ECC"
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default n
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depends on SPIRAM_MODE_OCT && SOC_SERIES_ESP32S3
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help
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Enable MSPI Error-Correcting Code function when accessing SPIRAM.
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If enabled, 1/16 of the SPI RAM total size will be reserved for error-correcting code.
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if SOC_SERIES_ESP32
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menu "PSRAM clock and cs IO for ESP32-DOWD"
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config D0WD_PSRAM_CLK_IO
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int "PSRAM CLK IO number"
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range 0 33
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default 17
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help
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The PSRAM CLOCK IO can be any unused GPIO, user can config it based on hardware design. If user use
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1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
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config D0WD_PSRAM_CS_IO
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int "PSRAM CS IO number"
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range 0 33
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default 16
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help
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The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. If user use
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1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
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endmenu # PSRAM clock and cs IO for ESP32-DOWD
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menu "PSRAM clock and cs IO for ESP32-D2WD"
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config D2WD_PSRAM_CLK_IO
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int "PSRAM CLK IO number"
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range 0 33
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default 9
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help
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User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram,
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so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
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config D2WD_PSRAM_CS_IO
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int "PSRAM CS IO number"
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range 0 33
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default 10
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help
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User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram,
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so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
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endmenu # PSRAM clock and cs IO for ESP32-D2WD
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menu "PSRAM clock and cs IO for ESP32-PICO"
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config PICO_PSRAM_CS_IO
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int "PSRAM CS IO number"
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range 0 33
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default 10
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help
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The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design.
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For ESP32-PICO chip, the psram share clock with flash, so user do not need to configure the clock
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IO For the reference hardware design, please refer to
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https://www.espressif.com/sites/default/files/documentation/esp32-pico-d4_datasheet_en.pdf
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endmenu # PSRAM clock and cs IO for ESP32-PICO
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config SPIRAM_CUSTOM_SPIWP_SD3_PIN
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bool "Use custom SPI PSRAM WP(SD3) Pin when flash pins set in eFuse (read help)"
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depends on ESPTOOLPY_FLASHMODE_DIO || ESPTOOLPY_FLASHMODE_DOUT
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default n
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help
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This setting is only used if the SPI flash pins have been overridden by setting the eFuses
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SPI_PAD_CONFIG_xxx, and the SPI flash mode is DIO or DOUT.
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When this is the case, the eFuse config only defines 3 of the 4 Quad I/O data pins. The WP pin (aka
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ESP32 pin "SD_DATA_3" or SPI flash pin "IO2") is not specified in eFuse. The psram only has QPI
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mode, so a WP pin setting is necessary.
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If this config item is set to N (default), the correct WP pin will be automatically used for any
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Espressif chip or module with integrated flash. If a custom setting is needed, set this config item
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to Y and specify the GPIO number connected to the WP pin.
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When flash mode is set to QIO or QOUT, the PSRAM WP pin will be set the same as the SPI Flash WP pin
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configured in the bootloader.
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config SPIRAM_SPIWP_SD3_PIN
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int "Custom SPI PSRAM WP(SD3) Pin"
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depends on SPIRAM_CUSTOM_SPIWP_SD3_PIN
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range 0 33
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default 7
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help
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The option "Use custom SPI PSRAM WP(SD3) pin" must be set or this value is ignored
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If burning a customized set of SPI flash pins in eFuse and using DIO or DOUT mode for flash, set this
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value to the GPIO number of the SPIRAM WP pin.
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endif # SOC_SERIES_ESP32
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endmenu # ESP_SPIRAM
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endif # SOC_SERIES_ESP32 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3
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