29 lines
447 B
Plaintext
29 lines
447 B
Plaintext
/*
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* Copyright 2022 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/ {
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soc {
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sram: sram@400000 {
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ranges = <0x4000000 0x4000000 0x20000000>;
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};
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peripheral: peripheral@40000000 {
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ranges = <0x0 0x40000000 0x10000000>;
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};
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};
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};
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#include "nxp_lpc55S3x_common.dtsi"
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/*
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* lpc55S_36:
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* Combine SRAM0, SRAM1, SRAM2, SRAM3, SRAM4 for total of 112K RAM
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*/
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&sram0 {
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compatible = "mmio-sram";
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reg = <0x20000000 DT_SIZE_K(112)>;
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};
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