444 lines
10 KiB
C
444 lines
10 KiB
C
/*
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* Copyright (c) 2020 Geanix ApS
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT microchip_mcp23s17
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/**
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* @file Driver for MCP23S17 SPI-based GPIO driver.
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*/
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#include <errno.h>
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#include <kernel.h>
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#include <device.h>
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#include <init.h>
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#include <sys/byteorder.h>
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#include <drivers/gpio.h>
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#include <drivers/spi.h>
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#include "gpio_utils.h"
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#include "gpio_mcp23s17.h"
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#define LOG_LEVEL CONFIG_GPIO_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(gpio_mcp23s17);
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/**
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* @brief Read both port 0 and port 1 registers of certain register function.
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*
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* Given the register in reg, read the pair of port 0 and port 1.
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*
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* @param dev Device struct of the MCP23S17.
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* @param reg Register to read (the PORTA of the pair of registers).
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* @param buf Buffer to read data into.
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*
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* @return 0 if successful, failed otherwise.
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*/
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static int read_port_regs(struct device *dev, u8_t reg, u16_t *buf)
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{
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struct mcp23s17_drv_data *const drv_data =
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(struct mcp23s17_drv_data *const)dev->driver_data;
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int ret;
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u16_t port_data;
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u8_t addr = MCP23S17_ADDR | MCP23S17_READBIT;
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u8_t buffer_tx[4] = { addr, reg, 0, 0 };
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const struct spi_buf tx_buf = {
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.buf = buffer_tx,
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.len = 4,
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};
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const struct spi_buf_set tx = {
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.buffers = &tx_buf,
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.count = 1,
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};
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const struct spi_buf rx_buf[2] = {
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{
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.buf = NULL,
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.len = 2
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},
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{
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.buf = (u8_t *)&port_data,
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.len = 2
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}
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};
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const struct spi_buf_set rx = {
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.buffers = rx_buf,
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.count = ARRAY_SIZE(rx_buf),
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};
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ret = spi_transceive(drv_data->spi, &drv_data->spi_cfg, &tx, &rx);
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if (ret) {
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LOG_DBG("spi_transceive FAIL %d\n", ret);
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return ret;
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}
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*buf = sys_le16_to_cpu(port_data);
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LOG_DBG("MCP23S17: Read: REG[0x%X] = 0x%X, REG[0x%X] = 0x%X",
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reg, (*buf & 0xFF), (reg + 1), (*buf >> 8));
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return 0;
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}
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/**
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* @brief Write both port 0 and port 1 registers of certain register function.
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*
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* Given the register in reg, write the pair of port 0 and port 1.
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*
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* @param dev Device struct of the MCP23S17.
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* @param reg Register to write into (the PORTA of the pair of registers).
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* @param buf Buffer to write data from.
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*
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* @return 0 if successful, failed otherwise.
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*/
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static int write_port_regs(struct device *dev, u8_t reg, u16_t value)
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{
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struct mcp23s17_drv_data *const drv_data =
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(struct mcp23s17_drv_data *const)dev->driver_data;
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int ret;
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u16_t port_data;
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LOG_DBG("MCP23S17: Write: REG[0x%X] = 0x%X, REG[0x%X] = 0x%X",
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reg, (value & 0xFF), (reg + 1), (value >> 8));
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port_data = sys_cpu_to_le16(value);
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u8_t addr = MCP23S17_ADDR;
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u8_t buffer_tx[2] = { addr, reg };
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const struct spi_buf tx_buf[2] = {
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{
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.buf = buffer_tx,
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.len = 2,
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},
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{
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.buf = (u8_t *)&port_data,
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.len = 2,
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}
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};
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const struct spi_buf_set tx = {
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.buffers = tx_buf,
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.count = ARRAY_SIZE(tx_buf),
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};
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ret = spi_write(drv_data->spi, &drv_data->spi_cfg, &tx);
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if (ret) {
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LOG_DBG("spi_write FAIL %d\n", ret);
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return ret;
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}
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return 0;
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}
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/**
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* @brief Setup the pin direction (input or output)
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*
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* @param dev Device struct of the MCP23S17
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* @param pin The pin number
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* @param flags Flags of pin or port
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*
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* @return 0 if successful, failed otherwise
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*/
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static int setup_pin_dir(struct device *dev, u32_t pin, int flags)
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{
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struct mcp23s17_drv_data *const drv_data =
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(struct mcp23s17_drv_data *const)dev->driver_data;
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u16_t *dir = &drv_data->reg_cache.iodir;
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u16_t *output = &drv_data->reg_cache.gpio;
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int ret;
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if ((flags & GPIO_OUTPUT) != 0U) {
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if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0U) {
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*output |= BIT(pin);
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} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0U) {
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*output &= ~BIT(pin);
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}
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*dir &= ~BIT(pin);
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} else {
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*dir |= BIT(pin);
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}
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ret = write_port_regs(dev, REG_GPIO_PORTA, *output);
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if (ret != 0) {
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return ret;
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}
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ret = write_port_regs(dev, REG_IODIR_PORTA, *dir);
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return ret;
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}
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/**
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* @brief Setup the pin pull up/pull down status
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*
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* @param dev Device struct of the MCP23S17
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* @param pin The pin number
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* @param flags Flags of pin or port
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*
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* @return 0 if successful, failed otherwise
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*/
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static int setup_pin_pullupdown(struct device *dev, u32_t pin, int flags)
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{
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struct mcp23s17_drv_data *const drv_data =
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(struct mcp23s17_drv_data *const)dev->driver_data;
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u16_t port;
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int ret;
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/* Setup pin pull up or pull down */
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port = drv_data->reg_cache.gppu;
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/* pull down == 0, pull up == 1 */
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if ((flags & GPIO_PULL_DOWN) != 0U) {
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return -ENOTSUP;
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}
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WRITE_BIT(port, pin, (flags & GPIO_PULL_UP) != 0U);
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ret = write_port_regs(dev, REG_GPPU_PORTA, port);
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if (ret == 0) {
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drv_data->reg_cache.gppu = port;
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}
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return ret;
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}
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static int mcp23s17_config(struct device *dev,
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gpio_pin_t pin, gpio_flags_t flags)
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{
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struct mcp23s17_drv_data *const drv_data =
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(struct mcp23s17_drv_data *const)dev->driver_data;
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int ret;
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/* Can't do SPI bus operations from an ISR */
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if (k_is_in_isr()) {
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return -EWOULDBLOCK;
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}
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k_sem_take(&drv_data->lock, K_FOREVER);
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if ((flags & GPIO_OPEN_DRAIN) != 0U) {
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ret = -ENOTSUP;
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goto done;
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};
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ret = setup_pin_dir(dev, pin, flags);
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if (ret) {
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LOG_ERR("MCP23S17: error setting pin direction (%d)", ret);
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goto done;
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}
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ret = setup_pin_pullupdown(dev, pin, flags);
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if (ret) {
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LOG_ERR("MCP23S17: error setting pin pull up/down (%d)", ret);
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goto done;
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}
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done:
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k_sem_give(&drv_data->lock);
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return ret;
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}
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static int mcp23s17_port_get_raw(struct device *dev, u32_t *value)
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{
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struct mcp23s17_drv_data *const drv_data =
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(struct mcp23s17_drv_data *const)dev->driver_data;
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u16_t buf;
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int ret;
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/* Can't do SPI bus operations from an ISR */
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if (k_is_in_isr()) {
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return -EWOULDBLOCK;
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}
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k_sem_take(&drv_data->lock, K_FOREVER);
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ret = read_port_regs(dev, REG_GPIO_PORTA, &buf);
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if (ret != 0) {
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goto done;
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}
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*value = buf;
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done:
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k_sem_give(&drv_data->lock);
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return ret;
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}
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static int mcp23s17_port_set_masked_raw(struct device *dev,
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u32_t mask, u32_t value)
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{
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struct mcp23s17_drv_data *const drv_data =
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(struct mcp23s17_drv_data *const)dev->driver_data;
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u16_t buf;
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int ret;
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/* Can't do SPI bus operations from an ISR */
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if (k_is_in_isr()) {
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return -EWOULDBLOCK;
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}
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k_sem_take(&drv_data->lock, K_FOREVER);
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buf = drv_data->reg_cache.gpio;
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buf = (buf & ~mask) | (mask & value);
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ret = write_port_regs(dev, REG_GPIO_PORTA, buf);
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if (ret == 0) {
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drv_data->reg_cache.gpio = buf;
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}
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k_sem_give(&drv_data->lock);
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return ret;
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}
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static int mcp23s17_port_set_bits_raw(struct device *dev, u32_t mask)
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{
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return mcp23s17_port_set_masked_raw(dev, mask, mask);
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}
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static int mcp23s17_port_clear_bits_raw(struct device *dev, u32_t mask)
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{
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return mcp23s17_port_set_masked_raw(dev, mask, 0);
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}
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static int mcp23s17_port_toggle_bits(struct device *dev, u32_t mask)
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{
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struct mcp23s17_drv_data *const drv_data =
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(struct mcp23s17_drv_data *const)dev->driver_data;
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u16_t buf;
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int ret;
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/* Can't do SPI bus operations from an ISR */
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if (k_is_in_isr()) {
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return -EWOULDBLOCK;
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}
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k_sem_take(&drv_data->lock, K_FOREVER);
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buf = drv_data->reg_cache.gpio;
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buf ^= mask;
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ret = write_port_regs(dev, REG_GPIO_PORTA, buf);
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if (ret == 0) {
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drv_data->reg_cache.gpio = buf;
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}
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k_sem_give(&drv_data->lock);
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return ret;
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}
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static int mcp23s17_pin_interrupt_configure(struct device *dev,
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gpio_pin_t pin,
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enum gpio_int_mode mode,
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enum gpio_int_trig trig)
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{
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return -ENOTSUP;
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}
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static const struct gpio_driver_api api_table = {
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.pin_configure = mcp23s17_config,
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.port_get_raw = mcp23s17_port_get_raw,
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.port_set_masked_raw = mcp23s17_port_set_masked_raw,
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.port_set_bits_raw = mcp23s17_port_set_bits_raw,
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.port_clear_bits_raw = mcp23s17_port_clear_bits_raw,
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.port_toggle_bits = mcp23s17_port_toggle_bits,
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.pin_interrupt_configure = mcp23s17_pin_interrupt_configure,
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};
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/**
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* @brief Initialization function of MCP23S17
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*
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* @param dev Device struct
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* @return 0 if successful, failed otherwise.
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*/
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static int mcp23s17_init(struct device *dev)
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{
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const struct mcp23s17_config *const config =
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dev->config_info;
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struct mcp23s17_drv_data *const drv_data =
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(struct mcp23s17_drv_data *const)dev->driver_data;
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drv_data->spi = device_get_binding((char *)config->spi_dev_name);
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if (!drv_data->spi) {
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LOG_DBG("Unable to get SPI device");
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return -ENODEV;
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}
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if (config->cs_dev) {
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/* handle SPI CS thru GPIO if it is the case */
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drv_data->mcp23s17_cs_ctrl.gpio_dev =
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device_get_binding(config->cs_dev);
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if (!drv_data->mcp23s17_cs_ctrl.gpio_dev) {
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LOG_ERR("Unable to get GPIO SPI CS device");
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return -ENODEV;
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}
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drv_data->mcp23s17_cs_ctrl.gpio_pin = config->cs_pin;
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drv_data->mcp23s17_cs_ctrl.delay = 0;
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drv_data->spi_cfg.cs = &drv_data->mcp23s17_cs_ctrl;
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LOG_DBG("SPI GPIO CS configured on %s:%u",
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config->cs_dev, config->cs_pin);
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}
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drv_data->spi_cfg.frequency = config->freq;
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drv_data->spi_cfg.operation = (SPI_OP_MODE_MASTER | SPI_MODE_CPOL |
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SPI_MODE_CPHA | SPI_WORD_SET(8) |
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SPI_LINES_SINGLE);
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drv_data->spi_cfg.slave = config->slave;
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k_sem_init(&drv_data->lock, 1, 1);
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return 0;
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}
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#define MCP23S17_INIT(inst) \
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static struct mcp23s17_config mcp23s17_##inst##_config = { \
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.common = { \
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.port_pin_mask = \
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GPIO_PORT_PIN_MASK_FROM_DT_INST(inst), \
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}, \
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.spi_dev_name = DT_INST_BUS_LABEL(inst), \
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.slave = DT_INST_REG_ADDR(inst), \
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.freq = DT_INST_PROP(inst, spi_max_frequency), \
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\
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IF_ENABLED(DT_INST_SPI_DEV_HAS_CS_GPIOS(inst), \
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(.cs_dev = \
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DT_INST_SPI_DEV_CS_GPIOS_LABEL(inst),)) \
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IF_ENABLED(DT_INST_SPI_DEV_HAS_CS_GPIOS(inst), \
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(.cs_pin = \
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DT_INST_SPI_DEV_CS_GPIOS_PIN(inst),)) \
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}; \
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\
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static struct mcp23s17_drv_data mcp23s17_##inst##_drvdata = { \
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/* Default for registers according to datasheet */ \
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.reg_cache.iodir = 0xFFFF, \
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.reg_cache.ipol = 0x0, \
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.reg_cache.gpinten = 0x0, \
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.reg_cache.defval = 0x0, \
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.reg_cache.intcon = 0x0, \
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.reg_cache.iocon = 0x0, \
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.reg_cache.gppu = 0x0, \
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.reg_cache.intf = 0x0, \
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.reg_cache.intcap = 0x0, \
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.reg_cache.gpio = 0x0, \
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.reg_cache.olat = 0x0, \
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}; \
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\
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/* This has to init after SPI master */ \
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DEVICE_AND_API_INIT(mcp23s17_##inst, DT_INST_LABEL(inst), \
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mcp23s17_init, &mcp23s17_##inst##_drvdata, \
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&mcp23s17_##inst##_config, \
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POST_KERNEL, \
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CONFIG_GPIO_MCP23S17_INIT_PRIORITY, \
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&api_table);
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DT_INST_FOREACH_STATUS_OKAY(MCP23S17_INIT)
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