45 lines
1.4 KiB
Verilog
45 lines
1.4 KiB
Verilog
module ghrd_10m50da_top (
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//Clock and Reset
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input wire clk_50,
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input wire fpga_reset_n,
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//QSPI
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// output wire qspi_clk,
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// inout wire[3:0] qspi_io,
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// output wire qspi_csn,
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//16550 UART
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input wire uart_rx,
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output wire uart_tx,
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output wire [4:0] user_led
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);
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//Heart-beat counter
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reg [25:0] heart_beat_cnt;
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// SoC sub-system module
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ghrd_10m50da ghrd_10m50da_inst (
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.clk_clk (clk_50),
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.reset_reset_n (fpga_reset_n),
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// .ext_flash_flash_dataout_conduit_dataout (qspi_io),
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// .ext_flash_flash_dclk_out_conduit_dclk_out (qspi_clk),
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// .ext_flash_flash_ncs_conduit_ncs (qspi_csn),
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//16550 UART
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.a_16550_uart_0_rs_232_serial_sin (uart_rx), // a_16550_uart_0_rs_232_serial.sin
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.a_16550_uart_0_rs_232_serial_sout (uart_tx), // .sout
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.a_16550_uart_0_rs_232_serial_sout_oe () // .sout_oe
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);
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//Heart beat by 50MHz clock
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always @(posedge clk_50 or negedge fpga_reset_n)
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if (!fpga_reset_n)
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heart_beat_cnt <= 26'h0; //0x3FFFFFF
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else
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heart_beat_cnt <= heart_beat_cnt + 1'b1;
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assign user_led = {4'hf,heart_beat_cnt[25]};
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endmodule
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