99 lines
1.7 KiB
Plaintext
99 lines
1.7 KiB
Plaintext
/*
|
|
* Copyright (c) 2018 Nordic Semiconductor ASA
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
#include <arm/armv8-m.dtsi>
|
|
#include <dt-bindings/i2c/i2c.h>
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
|
|
/ {
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-m33f";
|
|
reg = <0>;
|
|
};
|
|
};
|
|
|
|
sram0: memory@20000000 {
|
|
device_type = "memory";
|
|
compatible = "mmio-sram";
|
|
};
|
|
|
|
aliases {
|
|
flash-controller = &flash_controller;
|
|
ficr = &ficr;
|
|
rtc-0 = &rtc0;
|
|
rtc-1 = &rtc1;
|
|
clock = &clock;
|
|
power = &power;
|
|
nvmc = &flash_controller;
|
|
spu = &spu;
|
|
uart-0 = &uart0;
|
|
uart-1 = &uart1;
|
|
uart-2 = &uart2;
|
|
uart-3 = &uart3;
|
|
adc-0 = &adc;
|
|
gpio-0 = &gpio0;
|
|
gpiote-0 = &gpiote;
|
|
i2c-0 = &i2c0;
|
|
i2c-1 = &i2c1;
|
|
i2c-2 = &i2c2;
|
|
i2c-3 = &i2c3;
|
|
spi-0 = &spi0;
|
|
spi-1 = &spi1;
|
|
spi-2 = &spi2;
|
|
spi-3 = &spi3;
|
|
pwm-0 = &pwm0;
|
|
pwm-1 = &pwm1;
|
|
pwm-2 = &pwm2;
|
|
pwm-3 = &pwm3;
|
|
wdt-0 = &wdt;
|
|
timer-0 = &timer0;
|
|
timer-1 = &timer1;
|
|
timer-2 = &timer2;
|
|
};
|
|
|
|
soc {
|
|
peripheral@50000000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x50000000 0x10000000>;
|
|
|
|
/* Common nRF9160 peripheral description */
|
|
#include "nrf9160_common.dtsi"
|
|
};
|
|
|
|
/* Addditional Secure peripherals */
|
|
gpiote: gpiote@5000d000 {
|
|
compatible = "nordic,nrf-gpiote";
|
|
reg = <0x5000d000 0x1000>;
|
|
interrupts = <13 5>;
|
|
status = "disabled";
|
|
label = "GPIOTE_0";
|
|
};
|
|
|
|
spu: spu@50003000 {
|
|
compatible = "nordic,nrf-spu";
|
|
reg = <0x50003000 0x1000>;
|
|
interrupts = <3 1>;
|
|
status = "ok";
|
|
};
|
|
|
|
ficr: ficr@ff0000 {
|
|
compatible = "nordic,nrf-ficr";
|
|
reg = <0xff0000 0x1000>;
|
|
status = "ok";
|
|
};
|
|
};
|
|
};
|
|
|
|
&nvic {
|
|
arm,num-irq-priority-bits = <3>;
|
|
};
|