Antony Pavlov e44052f25a dts: riscv32: rv32m1: fix reg value for cpu@1 ... The second cpu core has to have reg = <1>. See, for example, dts/xtensa/esp32.dtsi. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>		2019-05-07 08:39:27 -04:00
..
arc	boards: iotdk: add mpu and fpu configuration	2019-04-29 09:03:24 -07:00
arm	soc: ti_simplelink: add support for TI CC13x2 / CC26x2 series	2019-05-04 09:13:43 -05:00
bindings	soc: ti_simplelink: add support for TI CC13x2 / CC26x2 series	2019-05-04 09:13:43 -05:00
common	dts: flash simulator cleanup	2019-04-26 04:04:19 -07:00
nios2	license: cleanup: add SPDX Apache-2.0 license identifier	2019-04-07 08:45:22 -04:00
riscv32	dts: riscv32: rv32m1: fix reg value for cpu@1	2019-05-07 08:39:27 -04:00
x86	boards/x86/up_squared: move UART configuration to apollo_lake.dtsi	2019-05-04 18:29:32 -04:00
xtensa	license: cleanup: add SPDX Apache-2.0 license identifier	2019-04-07 08:45:22 -04:00
Kconfig	license: cleanup: add SPDX Apache-2.0 license identifier	2019-04-07 08:45:22 -04:00