143 lines
3.6 KiB
C
143 lines
3.6 KiB
C
/*
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* Copyright (c) 2018 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <sw_isr_table.h>
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#include <arch/cpu.h>
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#include <sys/__assert.h>
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/*
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* Common code for arches that use software ISR tables (CONFIG_GEN_ISR_TABLES)
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*/
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#ifdef CONFIG_DYNAMIC_INTERRUPTS
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#ifdef CONFIG_MULTI_LEVEL_INTERRUPTS
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struct irq_parent_offset {
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unsigned int irq;
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unsigned int offset;
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};
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#define INIT_IRQ_PARENT_OFFSET(i, o) { \
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.irq = i, \
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.offset = o, \
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},
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#define IRQ_INDEX_TO_OFFSET(i, base) (base + i * CONFIG_MAX_IRQ_PER_AGGREGATOR)
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#ifdef CONFIG_2ND_LEVEL_INTERRUPTS
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#define CAT_2ND_LVL_LIST(i, base) \
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INIT_IRQ_PARENT_OFFSET(CONFIG_2ND_LVL_INTR_0##i##_OFFSET, \
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IRQ_INDEX_TO_OFFSET(i, base))
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static struct irq_parent_offset lvl2_irq_list[CONFIG_NUM_2ND_LEVEL_AGGREGATORS]
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= { UTIL_LISTIFY(CONFIG_NUM_2ND_LEVEL_AGGREGATORS, CAT_2ND_LVL_LIST,
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CONFIG_2ND_LVL_ISR_TBL_OFFSET) };
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#endif/* CONFIG_2ND_LEVEL_INTERRUPTS */
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#ifdef CONFIG_3RD_LEVEL_INTERRUPTS
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#define CAT_3RD_LVL_LIST(i, base) \
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INIT_IRQ_PARENT_OFFSET(CONFIG_3RD_LVL_INTR_0##i##_OFFSET, \
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IRQ_INDEX_TO_OFFSET(i, base))
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static struct irq_parent_offset lvl3_irq_list[CONFIG_NUM_3RD_LEVEL_AGGREGATORS]
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= { UTIL_LISTIFY(CONFIG_NUM_3RD_LEVEL_AGGREGATORS, CAT_3RD_LVL_LIST,
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CONFIG_3RD_LVL_ISR_TBL_OFFSET) };
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#endif /* CONFIG_3RD_LEVEL_INTERRUPTS */
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unsigned int get_parent_offset(unsigned int parent_irq,
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struct irq_parent_offset list[],
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unsigned int length)
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{
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unsigned int i;
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unsigned int offset = 0;
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for (i = 0; i < length; ++i) {
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if (list[i].irq == parent_irq) {
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offset = list[i].offset;
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break;
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}
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}
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__ASSERT(i != length, "Invalid argument: %i", parent_irq);
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return offset;
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}
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#endif /* CONFIG_MULTI_LEVEL_INTERRUPTS */
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void z_isr_install(unsigned int irq, void (*routine)(const void *),
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const void *param)
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{
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unsigned int table_idx;
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/*
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* Do not assert on the IRQ enable status for ARM GIC since the SGI
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* type interrupts are always enabled and attempting to install an ISR
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* for them will cause the assertion to fail.
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*/
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#ifndef CONFIG_GIC
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__ASSERT(!irq_is_enabled(irq), "IRQ %d is enabled", irq);
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#endif /* !CONFIG_GIC */
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#ifdef CONFIG_MULTI_LEVEL_INTERRUPTS
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unsigned int level;
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unsigned int parent_irq;
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unsigned int parent_offset;
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level = irq_get_level(irq);
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if (level == 2) {
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parent_irq = irq_parent_level_2(irq);
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parent_offset = get_parent_offset(parent_irq,
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lvl2_irq_list,
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CONFIG_NUM_2ND_LEVEL_AGGREGATORS);
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table_idx = parent_offset + irq_from_level_2(irq);
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}
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#ifdef CONFIG_3RD_LEVEL_INTERRUPTS
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else if (level == 3) {
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parent_irq = irq_parent_level_3(irq);
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parent_offset = get_parent_offset(parent_irq,
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lvl3_irq_list,
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CONFIG_NUM_3RD_LEVEL_AGGREGATORS);
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table_idx = parent_offset + irq_from_level_3(irq);
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}
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#endif /* CONFIG_3RD_LEVEL_INTERRUPTS */
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else {
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table_idx = irq;
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}
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table_idx -= CONFIG_GEN_IRQ_START_VECTOR;
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#else
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table_idx = irq - CONFIG_GEN_IRQ_START_VECTOR;
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#endif /* CONFIG_MULTI_LEVEL_INTERRUPTS */
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/* If dynamic IRQs are enabled, then the _sw_isr_table is in RAM and
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* can be modified
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*/
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_sw_isr_table[table_idx].arg = param;
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_sw_isr_table[table_idx].isr = routine;
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}
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/* Some architectures don't/can't interpret flags or priority and have
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* no more processing to do than this. Provide a generic fallback.
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*/
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int __weak arch_irq_connect_dynamic(unsigned int irq,
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unsigned int priority,
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void (*routine)(const void *),
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const void *parameter,
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uint32_t flags)
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{
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ARG_UNUSED(flags);
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ARG_UNUSED(priority);
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z_isr_install(irq, routine, parameter);
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return irq;
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}
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#endif /* CONFIG_DYNAMIC_INTERRUPTS */
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