zephyr/arch/common
Anas Nashif 6e27478c3d benchmarking: remove execution benchmarking code
This code had one purpose only, feed timing information into a test and
was not used by anything else. The custom trace points unfortunatly were
not accurate and this test was delivering informatin that conflicted
with other tests we have due to placement of such trace points in the
architecture and kernel code.

For such measurements we are planning to use the tracing functionality
in a special mode that would be used for metrics without polluting the
architecture and kernel code with additional tracing and timing code.

Furthermore, much of the assembly code used had issues.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2020-09-05 13:28:38 -05:00
..
CMakeLists.txt benchmarking: remove execution benchmarking code 2020-09-05 13:28:38 -05:00
gen_isr_tables.py irq: Change dynamic API to take a constant parameter 2020-09-02 13:48:13 +02:00
isr_tables.c irq: Change dynamic API to take a constant parameter 2020-09-02 13:48:13 +02:00
nocache.ld arch: common: nocache: fix linker section definition 2019-06-19 09:08:40 -07:00
ramfunc.ld arch: Port the ramfunc section to the Cmake function 2019-05-20 22:28:28 -04:00
rom_start_offset.ld config: Rename TEXT_SECTION_OFFSET to ROM_START_OFFSET 2020-07-09 14:02:38 -04:00
sw_isr_common.c arch: Apply dynamic IRQ API change 2020-09-02 13:48:13 +02:00
timing.c arch: default timings for all architectures 2020-09-05 13:28:38 -05:00