707 lines
16 KiB
Plaintext
707 lines
16 KiB
Plaintext
# Kconfig - GPIO configuration options
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#
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# Copyright (c) 2015 Intel Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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menuconfig GPIO
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bool
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prompt "GPIO Drivers"
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default n
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help
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Include GPIO drivers in system config
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if GPIO
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config GPIO_DEBUG
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bool
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prompt "Debug output for GPIO drivers"
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default n
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depends on GPIO
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help
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Enable the debug output for GPIO drivers
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config GPIO_DW
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prompt "Designware GPIO"
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default n
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depends on GPIO
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bool
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help
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Enable driver for Designware GPIO
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config GPIO_DW_IO_ACCESS
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prompt "I/O register access"
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default y if ARC
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default n
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bool
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help
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Driver access configuration register by
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I/O or auxiliary registers.
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config GPIO_DW_BOTHEDGES_SUPPORT
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bool
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prompt "Interrupt on Both Edges"
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default y
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depends on GPIO_DW && !ARC
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help
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This option is enabled by platforms that
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supports the interrupt-both-edges feature.
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This feature allows the GPIO hardware to
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trigger and interrupt on both, falling and
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rising, edges of an input.
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config GPIO_DW_SHARED_IRQ
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bool
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default n
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depends on GPIO_DW
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config GPIO_DW_VENDOR_ID
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hex "PCI Vendor ID"
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depends on GPIO_DW && PCI
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default 0x8086
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config GPIO_DW_DEVICE_ID
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hex "PCI Device ID"
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depends on GPIO_DW && PCI
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default 0x934
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config GPIO_DW_CLASS
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hex "PCI class"
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depends on GPIO_DW && PCI
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default 0x0C
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config GPIO_DW_INIT_PRIORITY
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int
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default 60
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prompt "Init priority"
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help
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Device driver initialization priority.
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config GPIO_DW_CLOCK_GATE
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bool "Enable glock gating"
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depends on GPIO_DW
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select CLOCK_CONTROL
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default n
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config GPIO_DW_CLOCK_GATE_DRV_NAME
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string
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depends on GPIO_DW_CLOCK_GATE
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default ""
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config GPIO_DW_0
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bool "Designware GPIO block 0"
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depends on GPIO_DW
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default n
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help
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Include Designware GPIO driver
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config GPIO_DW_0_NAME
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string "Driver name"
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depends on GPIO_DW_0
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default "GPIO_0"
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config GPIO_DW_0_BASE_ADDR
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hex "Controller base address"
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depends on GPIO_DW_0
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default 0x00000000
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config GPIO_DW_0_BUS
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int "Port 0 PCI Bus"
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depends on GPIO_DW_0 && PCI
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default 0
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config GPIO_DW_0_DEV
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int "Port 0 PCI Dev"
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depends on GPIO_DW_0 && PCI
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default 0
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config GPIO_DW_0_FUNCTION
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int "PCI function number"
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depends on GPIO_DW_0 && PCI
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default 0
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config GPIO_DW_0_BAR
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int "PCI BAR slot"
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depends on GPIO_DW_0 && PCI
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default 0
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config GPIO_DW_0_BITS
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int "number of pins controlled"
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depends on GPIO_DW_0
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default 32
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help
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Number of pins controlled by controller
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config GPIO_DW_0_CLOCK_GATE_SUBSYS
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int "Clock controller's subsystem"
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depends on GPIO_DW_CLOCK_GATE && GPIO_DW_0
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default 0
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choice
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prompt "Port 0 Interrupts via"
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default GPIO_DW_0_IRQ_DIRECT
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depends on GPIO_DW_0
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config GPIO_DW_0_IRQ_DIRECT
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bool "Direct Hardware Interrupt"
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help
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When interrupts fire, the driver's ISR function is being called directly.
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config GPIO_DW_0_IRQ_SHARED
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bool "Shared IRQ"
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depends on SHARED_IRQ
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select GPIO_DW_SHARED_IRQ
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help
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When interrupts fire, the shared IRQ driver is notified. Then the shared IRQ
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driver dispatches the interrupt to other drivers.
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endchoice
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choice
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prompt "DW GPIO port 0 trigger condition"
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default GPIO_DW_0_RISING_EDGE
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depends on GPIO_DW_0 && GPIO_DW_0_IRQ_DIRECT
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config GPIO_DW_0_FALLING_EDGE
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bool "Falling edge"
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help
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DW GPIO port 0 uses falling edge interrupt
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config GPIO_DW_0_RISING_EDGE
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bool "Rising edge"
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help
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DW GPIO port 0 uses rising edge interrupt
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config GPIO_DW_0_LEVEL_HIGH
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bool "Level high"
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help
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DW GPIO port 0 uses level high interrupt
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config GPIO_DW_0_LEVEL_LOW
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bool "Level low"
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help
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DW GPIO port 0 uses level low interrupt
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endchoice
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config GPIO_DW_0_IRQ_SHARED_NAME
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string "Device name for Shared IRQ"
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depends on GPIO_DW_0 && GPIO_DW_0_IRQ_SHARED
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help
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Specify the device name for the shared IRQ driver. It is used to register
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this driver with the shared IRQ driver, so interrupts can be dispatched
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correctly.
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config GPIO_DW_0_IRQ
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int "Controller interrupt number"
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depends on GPIO_DW_0 && GPIO_DW_0_IRQ_DIRECT
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default 0
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help
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IRQ number for the controller
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config GPIO_DW_0_PRI
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int "Controller interrupt priority"
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depends on GPIO_DW_0 && GPIO_DW_0_IRQ_DIRECT
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default 2
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help
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IRQ priority
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config GPIO_DW_1
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bool "Designware GPIO block 1"
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depends on GPIO_DW
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default n
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help
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Include Designware GPIO driver
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config GPIO_DW_1_NAME
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string "Driver name"
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depends on GPIO_DW_1
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default "GPIO_1"
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config GPIO_DW_1_BASE_ADDR
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hex "Controller base address"
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depends on GPIO_DW_1
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default 0x00000000
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config GPIO_DW_1_BITS
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int "number of pins controlled"
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depends on GPIO_DW_1
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default 32
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help
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Number of pins controlled by controller
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config GPIO_DW_1_CLOCK_GATE_SUBSYS
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int "Clock controller's subsystem"
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depends on GPIO_DW_CLOCK_GATE && GPIO_DW_1
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default 0
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choice
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prompt "Port 1 Interrupts via"
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default GPIO_DW_1_IRQ_DIRECT
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depends on GPIO_DW_1
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config GPIO_DW_1_IRQ_DIRECT
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bool "Direct Hardware Interrupt"
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help
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When interrupts fire, the driver's ISR function is being called directly.
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config GPIO_DW_1_IRQ_SHARED
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bool "Shared IRQ"
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depends on SHARED_IRQ
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select GPIO_DW_SHARED_IRQ
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help
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When interrupts fire, the shared IRQ driver is notified. Then the shared IRQ
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driver dispatches the interrupt to other drivers.
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endchoice
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config GPIO_DW_1_IRQ_SHARED_NAME
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string "Device name for Shared IRQ"
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depends on GPIO_DW_1_IRQ_SHARED
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help
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Specify the device name for the shared IRQ driver. It is used to register
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this driver with the shared IRQ driver, so interrupts can be dispatched
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correctly.
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config GPIO_DW_1_IRQ
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int "Controller interrupt number"
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depends on GPIO_DW_1 && GPIO_DW_1_IRQ_DIRECT
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default 0
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help
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IRQ number for the controller
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config GPIO_DW_1_PRI
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int "Controller interrupt priority"
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depends on GPIO_DW_1 && GPIO_DW_1_IRQ_DIRECT
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default 2
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help
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IRQ priority
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choice
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prompt "DW GPIO port 1 trigger condition"
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default GPIO_DW_1_RISING_EDGE
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depends on GPIO_DW_1 && GPIO_DW_1_IRQ_DIRECT
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config GPIO_DW_1_FALLING_EDGE
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bool "Falling edge"
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help
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DW GPIO port 1 uses falling edge interrupt
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config GPIO_DW_1_RISING_EDGE
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bool "Rising edge"
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help
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DW GPIO port 1 uses rising edge interrupt
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config GPIO_DW_1_LEVEL_HIGH
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bool "Level high"
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help
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DW GPIO port 1 uses level high interrupt
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config GPIO_DW_1_LEVEL_LOW
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bool "Level low"
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help
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DW GPIO port 1 uses level low interrupt
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endchoice
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config GPIO_PCAL9535A
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bool "PCAL9535A I2C-based GPIO chip"
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depends on GPIO && I2C
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default n
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select NANO_TIMERS
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help
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Enable driver for PCAL9535A I2C-based GPIO chip.
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if GPIO_PCAL9535A
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config GPIO_PCAL9535A_DEBUG
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bool "Enable PCAL9535A Debugging"
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depends on GPIO_PCAL9535A
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default n
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help
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Enable debugging for PCAL9535A driver.
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config GPIO_PCAL9535A_INIT_PRIORITY
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int
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default 70
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prompt "Init priority"
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help
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Device driver initialization priority.
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config GPIO_PCAL9535A_0
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bool "PCAL9535A GPIO chip #0"
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depends on GPIO_PCAL9535A
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default n
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help
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Enable config options for the PCAL9535A I2C-based GPIO chip #0.
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config GPIO_PCAL9535A_0_DEV_NAME
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string "PCAL9535A GPIO chip #0 Device Name"
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depends on GPIO_PCAL9535A_0
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default "GPIO_P0"
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help
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Specify the device name for the PCAL9535A I2C-based GPIO chip #0.
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config GPIO_PCAL9535A_0_I2C_ADDR
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hex "PCAL9535A GPIO chip #0 I2C slave address"
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depends on GPIO_PCAL9535A_0
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default 0x0
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help
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Specify the I2C slave address for the PCAL9535A I2C-based GPIO chip #0.
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config GPIO_PCAL9535A_0_I2C_MASTER_DEV_NAME
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string "I2C Master where PCAL9535A GPIO chip #0 is connected"
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depends on GPIO_PCAL9535A_0
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default ""
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help
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Specify the device name of the I2C master device to which this
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PCAL9535A chip #0 is binded.
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config GPIO_PCAL9535A_1
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bool "PCAL9535A GPIO chip #1"
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depends on GPIO_PCAL9535A
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default n
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help
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Enable config options for the PCAL9535A I2C-based GPIO chip #1.
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config GPIO_PCAL9535A_1_DEV_NAME
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string "PCAL9535A GPIO chip #1 Device Name"
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depends on GPIO_PCAL9535A_1
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default "GPIO_P1"
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help
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Specify the device name for the PCAL9535A I2C-based GPIO chip #1.
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config GPIO_PCAL9535A_1_I2C_ADDR
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hex "PCAL9535A GPIO chip #1 I2C slave address"
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depends on GPIO_PCAL9535A_1
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default 0x0
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help
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Specify the I2C slave address for the PCAL9535A I2C-based GPIO chip #1.
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config GPIO_PCAL9535A_1_I2C_MASTER_DEV_NAME
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string "I2C Master where PCAL9535A GPIO chip #1 is connected"
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depends on GPIO_PCAL9535A_1
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default ""
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help
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Specify the device name of the I2C master device to which this
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PCAL9535A chip #1 is binded.
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config GPIO_PCAL9535A_2
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bool "PCAL9535A GPIO chip #2"
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depends on GPIO_PCAL9535A
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default n
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help
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Enable config options for the PCAL9535A I2C-based GPIO chip #2.
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config GPIO_PCAL9535A_2_DEV_NAME
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string "PCAL9535A GPIO chip #2 Device Name"
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depends on GPIO_PCAL9535A_2
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default "GPIO_P2"
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help
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Specify the device name for the PCAL9535A I2C-based GPIO chip #2.
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config GPIO_PCAL9535A_2_I2C_ADDR
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hex "PCAL9535A GPIO chip #2 I2C slave address"
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depends on GPIO_PCAL9535A_2
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default 0x0
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help
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Specify the I2C slave address for the PCAL9535A I2C-based GPIO chip #2.
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config GPIO_PCAL9535A_2_I2C_MASTER_DEV_NAME
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string "I2C Master where PCAL9535A GPIO chip #2 is connected"
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depends on GPIO_PCAL9535A_2
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default ""
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help
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Specify the device name of the I2C master device to which this
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PCAL9535A chip #2 is binded.
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config GPIO_PCAL9535A_3
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bool "PCAL9535A GPIO chip #3"
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depends on GPIO_PCAL9535A
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default n
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help
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Enable config options for the PCAL9535A I2C-based GPIO chip #3.
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config GPIO_PCAL9535A_3_DEV_NAME
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string "PCAL9535A GPIO chip #3 Device Name"
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depends on GPIO_PCAL9535A_3
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default "GPIO_P3"
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help
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Specify the device name for the PCAL9535A I2C-based GPIO chip #3.
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config GPIO_PCAL9535A_3_I2C_ADDR
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hex "PCAL9535A GPIO chip #3 I2C slave address"
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depends on GPIO_PCAL9535A_3
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default 0x0
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help
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Specify the I2C slave address for the PCAL9535A I2C-based GPIO chip #3.
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config GPIO_PCAL9535A_3_I2C_MASTER_DEV_NAME
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string "I2C Master where PCAL9535A GPIO chip #3 is connected"
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depends on GPIO_PCAL9535A_3
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default ""
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help
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Specify the device name of the I2C master device to which this
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PCAL9535A chip #3 is binded.
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endif #GPIO_PCAL9535A
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config GPIO_MMIO
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bool "MMIO-based GPIO driver"
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depends on GPIO
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default n
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help
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Enable driver for MMIO-based GPIOs.
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config GPIO_MMIO_INIT_PRIORITY
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int
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depends on GPIO_MMIO
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default 60
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prompt "Init priority"
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help
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Device driver initialization priority.
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config GPIO_MMIO_0
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bool "MMIO-based GPIO Port #0"
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depends on GPIO_MMIO
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default n
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help
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Enable config options for MMIO-based GPIO port #0.
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config GPIO_MMIO_0_DEV_NAME
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string "MMIO-based GPIO Port #0 Device Name"
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depends on GPIO_MMIO_0
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default "GPIO_M0"
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help
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Specify the device name.
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choice
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prompt "MMIO-based GPIO Port #0 Access Method"
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default GPIO_MMIO_0_ACCESS_MM
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depends on GPIO_MMIO_0
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config GPIO_MMIO_0_ACCESS_MM
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bool "Direct Memory Access"
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config GPIO_MMIO_0_ACCESS_IO
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bool "I/O Port"
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endchoice
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config GPIO_MMIO_0_CFG
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hex "MMIO-based GPIO Port #0 Configuration"
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depends on GPIO_MMIO_0
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default 0x0
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help
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Configuration for this GPIO port.
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Refer to <drivers/gpio/gpio-mmio.h> for more information.
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config GPIO_MMIO_0_EN
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hex "MMIO-based GPIO Port #0 Enable Register Address"
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depends on GPIO_MMIO_0
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default 0x0
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help
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The memory address for enable register.
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config GPIO_MMIO_0_DIR
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hex "MMIO-based GPIO Port #0 Direction Register Address"
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depends on GPIO_MMIO_0
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default 0x0
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help
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The memory address for direction register.
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config GPIO_MMIO_0_INPUT
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hex "MMIO-based GPIO Port #0 Input Pin Level Register Address"
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depends on GPIO_MMIO_0
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default 0x0
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help
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The memory address for input pin level register.
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config GPIO_MMIO_0_OUTPUT
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hex "MMIO-based GPIO Port #0 Output Pin Level Register Address"
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depends on GPIO_MMIO_0
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default 0x0
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help
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The memory address for output pin level register.
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config GPIO_MMIO_1
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bool "MMIO-based GPIO Port #1"
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depends on GPIO_MMIO
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default n
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help
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Enable config options for MMIO-based GPIO port #1.
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config GPIO_MMIO_1_DEV_NAME
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string "MMIO-based GPIO Port #1 Device Name"
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depends on GPIO_MMIO_1
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default "GPIO_M1"
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help
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Specify the device name.
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choice
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prompt "MMIO-based GPIO Port #1 Access Method"
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default GPIO_MMIO_1_ACCESS_MM
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depends on GPIO_MMIO_1
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config GPIO_MMIO_1_ACCESS_MM
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bool "Direct Memory Access"
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config GPIO_MMIO_1_ACCESS_IO
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bool "I/O Port"
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endchoice
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config GPIO_MMIO_1_CFG
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hex "MMIO-based GPIO Port #1 Configuration"
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depends on GPIO_MMIO_1
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default 0x0
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help
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Configuration for this GPIO port.
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Refer to <drivers/gpio/gpio-mmio.h> for more information.
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config GPIO_MMIO_1_EN
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hex "MMIO-based GPIO Port #1 Enable Register Address"
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depends on GPIO_MMIO_1
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default 0x0
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help
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The memory address for enable register.
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config GPIO_MMIO_1_DIR
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hex "MMIO-based GPIO Port #1 Direction Register Address"
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depends on GPIO_MMIO_1
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default 0x0
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help
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The memory address for direction register.
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config GPIO_MMIO_1_INPUT
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hex "MMIO-based GPIO Port #1 Input Pin Level Register Address"
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depends on GPIO_MMIO_1
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default 0x0
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help
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The memory address for input pin level register.
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config GPIO_MMIO_1_OUTPUT
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hex "MMIO-based GPIO Port #1 Output Pin Level Register Address"
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depends on GPIO_MMIO_1
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default 0x0
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help
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The memory address for output pin level register.
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config GPIO_QMSI
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bool "QMSI GPIO driver"
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depends on GPIO && QMSI_DRIVERS
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default n
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help
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Enable the GPIO driver found on Intel Microcontroller
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platforms, using the QMSI library.
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config GPIO_QMSI_0
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bool "QMSI GPIO block 0"
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depends on GPIO_QMSI
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default n
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help
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Include support for the GPIO port 0 using QMSI.
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config GPIO_QMSI_0_NAME
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string "Driver name"
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depends on GPIO_QMSI_0
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default "GPIO_0"
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config GPIO_QMSI_0_IRQ
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int "Controller interrupt number"
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depends on GPIO_QMSI_0
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default 0
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help
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IRQ number for the controller
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config GPIO_QMSI_0_PRI
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int "Controller interrupt priority"
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depends on GPIO_QMSI_0
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default 2
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help
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IRQ priority
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config GPIO_SCH
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bool "SCH GPIO controller"
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depends on GPIO
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default n
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help
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Enable the SCH GPIO driver found on Intel platforms
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config GPIO_SCH_INIT_PRIORITY
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int
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depends on GPIO_SCH
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default 60
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prompt "Init priority"
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help
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Device driver initialization priority.
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config GPIO_SCH_LEGACY_IO_PORTS_ACCESS
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bool "SCH registers accessed through legacy I/O ports"
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depends on GPIO_SCH
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default n
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help
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Enable the legacy I/O ports access methods for SCH registers.
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config GPIO_SCH_0
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bool "Enable SCH GPIO port 0"
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default 0
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depends on GPIO_SCH
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config GPIO_SCH_0_DEV_NAME
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string "Name of the device"
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depends on GPIO_SCH_0
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default "gpio_sch_0"
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config GPIO_SCH_0_BASE_ADDR
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hex "SCH GPIO base address"
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depends on GPIO_SCH_0
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default 0x0
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help
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The memory address where the memory mapped registers are found
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config GPIO_SCH_0_BITS
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int "Total of GPIO pins controlled"
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depends on GPIO_SCH_0
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default 0
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help
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The total of pins the controller can manage (CPU dependent)
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config GPIO_SCH_1
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bool "Enable SCH GPIO port 1"
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default n
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depends on GPIO_SCH
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config GPIO_SCH_1_DEV_NAME
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string "Name of the device"
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depends on GPIO_SCH_1
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default "gpio_sch_1"
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config GPIO_SCH_1_BASE_ADDR
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hex "SCH GPIO base address"
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depends on GPIO_SCH_1
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default 0x0
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help
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The memory address where the memory mapped registers are found
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config GPIO_SCH_1_BITS
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int "Total of GPIO pins controlled"
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depends on GPIO_SCH_1
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default 0
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help
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The total of pins the controller can manage (CPU dependent)
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endif # GPIO
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