Introduce the GPIO QMSI-based implementation. This is basically a
shim layer that implement's Zephyr's GPIO APIs on top of QMSI drivers.
This is an alternative driver that conflicts with the previous
GPIO_DW implementation. In order to enable it you must set:
- CONFIG_GPIO=n
- CONFIG_GPIO_QMSI=y
- CONFIG_GPIO_0=y
- CONFIG_QMSI_DRIVERS=y
- CONFIG_QMSI_INTALL_PATH="PATH_TO_QMSI"
Note that this driver currently only supports one controller instance,
GPIO_0. It is implemented this way due to a limitation from the current
version of QMSI. QMSI versions later than 1.0 doesn't have this
limitation.
Missing:
- support multiple controller instances (gpio_0, gpio_1, etc);
- enable level triggered interrupts in sync with system clock,
through setting INT_CLOCK_SYNC properly.
Change-Id: Ib61b153dae9741806a9a31d7dc1f82b96d000fbe
Signed-off-by: Jesus Sanchez-Palencia <jesus.sanchez-palencia@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
Use a default priority to avoid Kconfig blocking when priority
is not set in SoC or Board.
Change-Id: I4edda47b955a7ee834f04dc40d0decbd8dee6305
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Adds io/aux register support for IP configuration.
x86 and ARM configure IP through MMIO register access.
ARC architecture configure IP through io/aux register access.
Change-Id: I4d07b91af09d88b7eb6ac1aa02e875dcd626bd26
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
This is currently valid for quark_se platform. It's used internally to
suspend and/or resume the gpio controller.
Change-Id: I5147568ba6b0450363566b5f9fd2e8aa7e41df49
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Put initialization priorities as device driver Kconfig
parameter.
Initialization priority value for each platform is defined
in the platform Kconfig file.
Drivers and platform code use SYS_DEFINE_DEVICE to add
and initialization function.
Change-Id: I2f4f3c7370dac02408a1b50a0a1bade8b427a282
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
That fixes a build error. Platfom's board.h have to provide such flags
if they enable dw gpio 1 controller.
Take the opportunity to provide the right isr to IRQ_CONNECT_STATIC.
Change-Id: I16900ea04f7f7c5d3c99b93a92b00c1f651494de
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Such controller is found in legacy bridge on Intel's platforms. Such as
Poulsbo or Quark x1000.
Change-Id: I30f205f1e73aaa680092e92717fdacbb74046fa3
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Allows to remove the both edges support from the DW GPIO driver.
Change-Id: I9e39cca320aeac5d10aafe7a83641917ad004fe6
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
Changes the default IRQ priority level from 0 to 2 for the following
kernel configuration options as priorities 0 and 1 are reserved for the
first 32 IDT entries.
SHARED_IRQ_0_PRI
SHARED_IRQ_1_PRI
I2C_DW_0_INT_PRIORITY
GPIO_DW_0_PRI
GPIO_DW_1_PRI
SPI_INTEL_PORT_0_PRI
SPI_INTEL_PORT_1_PRI
Change-Id: I0fc821c68156eb1e1fe776b2bd4ff5890bba40e8
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Change all the Intel and Wind River code license from BSD-3 to Apache 2.
Change-Id: Id8be2c1c161a06ea8a0b9f38e17660e11dbb384b
Signed-off-by: Javier B Perez Hernandez <javier.b.perez.hernandez@linux.intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
On some platforms (e.g. Galileo), the GPIO controller is on PCI bus,
which shares IRQ with other devices (I2C on Galileo). This patch
adds support for utilizing shared IRQ.
Change-Id: I4b44bae15356e4710d54f0343fed1bd27f35e484
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add I/O port access to MMIO-based GPIO driver, in addition to
the existing direct memory access. This extends the driver,
so that it can address the registers through I/O read/write.
Change-Id: I53c74ad76472ac043764e33bfbb77a2bedc427fe
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add a Kconfig option to enable NANO_TIMERS for PCAL9535A.
Without enabling nano timers, compilation may fail.
Change-Id: If96358a17b9522f9323f3480b4716c3dfd82a3de
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds a simple driver for MMIO-based GPIO ports.
It does not trigger any interrupts due to pin level at this moment.
Change-Id: I0c439f221988817e4be72653c68257ef6ace5bde
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds the driver for I2C-based PCAL9535A GPIO chip.
This currently only enables minimal set of features of the chip for
very simple input/output operations, and does not support interrupt
yet.
Change-Id: I32ea07a71a38866280a96e68cff49cb0df12b85d
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This change puts the DW GPIO Kconfig selections inside GPIO menu.
This also groups all DW GPIO related selections under GPIO_DW.
Change-Id: I776f3f6b89e1a4dc366648f8290abb27de9eceb8
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
- Device ID was wrong
- Setting default class id
Change-Id: I9fd1df284eca4067c21beffa7599307a40be5144
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This will enable the possibility to use this driver with Quark X1000.
Change-Id: Ic40b750d608488e97cc7662cad6c6d66dbf428ab
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
[DL: captilize commit message title; fixed some whitespaces;
changed the __initconfig_gpio_* from level 0 to level 1,
which is the level of pure_init; and added include path
to board.h; ]
Change-Id: I7eea6a6ca9e4b7cf8d1ccabb57f07f786da93ef0
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Jesus Sanchez-Palencia