zephyr/arch/riscv
Stephanos Ioannidis 7751fbca44 arch: riscv: Align semihost_exec function at 16-byte boundary
QEMU requires that the semihosting trap instruction sequence, which
consists of three uncompressed instructions, lie in the same page, and
refuses to interpret the trap sequence if these instructions are placed
across two different pages.

This commit adds 16-byte alignment requirement to the `semihost_exec`
function, which occupies 12 bytes, to ensure that the three trap
sequence instructions in this function are never placed across two
different pages.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2022-08-08 10:52:34 +02:00
..
core arch: riscv: Align semihost_exec function at 16-byte boundary 2022-08-08 10:52:34 +02:00
include riscv: Introduce RISCV_ALWAYS_SWITCH_THROUGH_ECALL 2022-07-04 18:18:10 +02:00
CMakeLists.txt
Kconfig riscv: Use IRQ vector table for vectored mode 2022-07-07 10:00:20 +02:00
Kconfig.core riscv: Rework and cleanup Kconfig 2022-06-05 14:28:42 +02:00
Kconfig.isa riscv: Rework and cleanup Kconfig 2022-06-05 14:28:42 +02:00