Carlo Caione 7a11d883cc riscv: Introduce RISCV_ALWAYS_SWITCH_THROUGH_ECALL ... Some early RISC-V SoCs have a problem when an `mret` instruction is used outside a trap handler. After the latest Zephyr RISC-V huge rework, the arch_switch code is indeed calling `mret` when not in handler mode, breaking some early RISC-V platforms. Optionally restore the old behavior by adding a new CONFIG_RISCV_ALWAYS_SWITCH_THROUGH_ECALL symbol. Signed-off-by: Nicolas Pitre <npitre@baylibre.com> Signed-off-by: Carlo Caione <ccaione@baylibre.com>		2022-07-04 18:18:10 +02:00
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kernel_arch_data.h	arch: migrate includes to <zephyr/...>	2022-05-06 19:57:22 +02:00
kernel_arch_func.h	riscv: Introduce RISCV_ALWAYS_SWITCH_THROUGH_ECALL	2022-07-04 18:18:10 +02:00
offsets_short_arch.h	…
pmp.h	riscv: pmp: add new usermode support	2022-04-29 15:30:00 +02:00