571 lines
19 KiB
C
571 lines
19 KiB
C
/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#include <zephyr/irq.h>
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#include <zephyr/drivers/clock_control/renesas_ra_cgc.h>
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#include <zephyr/drivers/pwm.h>
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#include <zephyr/drivers/pinctrl.h>
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#include "r_gpt.h"
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#include "r_gpt_cfg.h"
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#include <zephyr/logging/log.h>
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#include <stdio.h>
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LOG_MODULE_REGISTER(pwm_renesas_ra8, CONFIG_PWM_LOG_LEVEL);
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#define DT_DRV_COMPAT renesas_ra8_pwm
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#define MAX_PIN 2U
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#define GPT_PRV_GTIO_HIGH_COMPARE_MATCH_LOW_CYCLE_END 0x6U
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#define GPT_PRV_GTIO_LOW_COMPARE_MATCH_HIGH_CYCLE_END 0x9U
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#define GPT_PRV_GTIOR_INITIAL_LEVEL_BIT 4
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#define GPT_PRV_GTIO_TOGGLE_COMPARE_MATCH 0x3U
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struct pwm_ra8_capture_data {
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pwm_capture_callback_handler_t callback;
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void *user_data;
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uint64_t period;
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uint64_t pulse;
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bool is_pulse_capture;
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bool is_busy;
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uint32_t overflows;
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bool continuous;
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};
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struct pwm_ra8_data {
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gpt_instance_ctrl_t fsp_ctrl;
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timer_cfg_t fsp_cfg;
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gpt_extended_cfg_t extend_cfg;
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uint16_t capture_a_event;
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uint16_t overflow_event;
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#ifdef CONFIG_PWM_CAPTURE
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struct pwm_ra8_capture_data capture;
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#endif /* CONFIG_PWM_CAPTURE */
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};
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struct pwm_ra8_config {
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const struct device *clock_dev;
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struct clock_control_ra_subsys_cfg clock_subsys;
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const struct pinctrl_dev_config *pincfg;
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};
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static uint32_t pwm_ra8_gtior_calculate(gpt_pin_level_t const stop_level)
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{
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/* The stop level is used as both the initial level and the stop level. */
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uint32_t gtior = R_GPT0_GTIOR_OAE_Msk | ((uint32_t)stop_level << R_GPT0_GTIOR_OADFLT_Pos) |
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((uint32_t)stop_level << GPT_PRV_GTIOR_INITIAL_LEVEL_BIT);
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uint32_t gtion = GPT_PRV_GTIO_LOW_COMPARE_MATCH_HIGH_CYCLE_END;
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/* Calculate the gtior value for PWM mode only */
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gtior |= gtion;
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return gtior;
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}
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static int pwm_ra8_apply_gtior_config(gpt_instance_ctrl_t *const p_ctrl,
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timer_cfg_t const *const p_cfg)
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{
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gpt_extended_cfg_t *p_extend = (gpt_extended_cfg_t *)p_cfg->p_extend;
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uint32_t gtior = p_extend->gtior_setting.gtior;
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#if GPT_CFG_OUTPUT_SUPPORT_ENABLE
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/* Check if custom GTIOR settings are provided. */
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if (p_extend->gtior_setting.gtior == 0) {
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/* If custom GTIOR settings are not provided, calculate GTIOR. */
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if (p_extend->gtioca.output_enabled) {
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uint32_t gtioca_gtior =
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pwm_ra8_gtior_calculate(p_extend->gtioca.stop_level);
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gtior |= gtioca_gtior << R_GPT0_GTIOR_GTIOA_Pos;
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}
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if (p_extend->gtiocb.output_enabled) {
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uint32_t gtiocb_gtior =
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pwm_ra8_gtior_calculate(p_extend->gtiocb.stop_level);
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gtior |= gtiocb_gtior << R_GPT0_GTIOR_GTIOB_Pos;
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}
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}
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#endif
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#if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE
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gpt_extended_pwm_cfg_t const *p_pwm_cfg = p_extend->p_pwm_cfg;
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if (NULL != p_pwm_cfg) {
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/* Check if custom GTIOR settings are provided. */
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if (p_extend->gtior_setting.gtior == 0) {
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/* If custom GTIOR settings are not provided, set gtioca_disable_settings
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* and gtiocb_disable_settings.
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*/
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gtior |= (uint32_t)(p_pwm_cfg->gtioca_disable_setting
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<< R_GPT0_GTIOR_OADF_Pos);
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gtior |= (uint32_t)(p_pwm_cfg->gtiocb_disable_setting
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<< R_GPT0_GTIOR_OBDF_Pos);
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}
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}
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#endif
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/* Check if custom GTIOR settings are provided. */
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if (p_extend->gtior_setting.gtior == 0) {
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/*
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* If custom GTIOR settings are not provided, configure the noise filter for
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* the GTIOC pins.
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*/
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gtior |= (uint32_t)(p_extend->capture_filter_gtioca << R_GPT0_GTIOR_NFAEN_Pos);
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gtior |= (uint32_t)(p_extend->capture_filter_gtiocb << R_GPT0_GTIOR_NFBEN_Pos);
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}
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/* Set the I/O control register. */
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p_ctrl->p_reg->GTIOR = gtior;
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return 0;
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}
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static int pwm_ra8_set_cycles(const struct device *dev, uint32_t pin, uint32_t period_cycles,
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uint32_t pulse_cycles, pwm_flags_t flags)
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{
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struct pwm_ra8_data *data = dev->data;
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uint32_t pulse;
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fsp_err_t err;
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if (pin >= MAX_PIN) {
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LOG_ERR("Only valid for gtioca and gtiocb pins");
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return -EINVAL;
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}
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if ((data->fsp_ctrl.variant == TIMER_VARIANT_16_BIT && period_cycles > UINT16_MAX) ||
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(data->fsp_ctrl.variant == TIMER_VARIANT_32_BIT && period_cycles > UINT32_MAX)) {
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LOG_ERR("Out of range period cycles are not valid");
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return -EINVAL;
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}
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/* gtioca and gtiocb setting */
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if (pin == GPT_IO_PIN_GTIOCA) {
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data->extend_cfg.gtioca.output_enabled = true;
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} else {
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data->extend_cfg.gtiocb.output_enabled = true;
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}
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pulse = (flags & PWM_POLARITY_INVERTED) ? period_cycles - pulse_cycles : pulse_cycles;
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/* Apply gtio output setting */
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pwm_ra8_apply_gtior_config(&data->fsp_ctrl, &data->fsp_cfg);
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/* Stop timer */
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err = R_GPT_Stop(&data->fsp_ctrl);
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if (err != FSP_SUCCESS) {
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return -EIO;
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}
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/* Update period cycles, reflected at an overflow */
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err = R_GPT_PeriodSet(&data->fsp_ctrl, period_cycles);
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if (err != FSP_SUCCESS) {
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return -EIO;
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}
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/* Update pulse cycles, reflected at an overflow */
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err = R_GPT_DutyCycleSet(&data->fsp_ctrl, pulse, pin);
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if (err != FSP_SUCCESS) {
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return -EIO;
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}
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/* Start timer */
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err = R_GPT_Start(&data->fsp_ctrl);
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if (err != FSP_SUCCESS) {
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return -EIO;
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}
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LOG_DBG("channel %u, pin %u, pulse %u, period %u, prescaler: %u.", data->fsp_cfg.channel,
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pin, pulse_cycles, period_cycles, data->fsp_cfg.source_div);
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return 0;
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};
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static int pwm_ra8_get_cycles_per_sec(const struct device *dev, uint32_t pin, uint64_t *cycles)
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{
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struct pwm_ra8_data *data = dev->data;
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timer_info_t info;
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fsp_err_t err;
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if (pin >= MAX_PIN) {
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LOG_ERR("Only valid for gtioca and gtiocb pins");
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return -EINVAL;
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}
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err = R_GPT_InfoGet(&data->fsp_ctrl, &info);
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if (err != FSP_SUCCESS) {
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return -EIO;
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}
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*cycles = (uint64_t)info.clock_frequency;
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return 0;
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};
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#ifdef CONFIG_PWM_CAPTURE
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extern void gpt_capture_compare_a_isr(void);
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extern void gpt_counter_overflow_isr(void);
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static void enable_irq(IRQn_Type const irq, uint32_t priority, void *p_context)
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{
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if (irq >= 0) {
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R_BSP_IrqCfgEnable(irq, priority, p_context);
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}
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}
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static void disable_irq(IRQn_Type irq)
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{
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/* Disable interrupts. */
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if (irq >= 0) {
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R_BSP_IrqDisable(irq);
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R_FSP_IsrContextSet(irq, NULL);
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}
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}
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static int pwm_ra8_configure_capture(const struct device *dev, uint32_t pin, pwm_flags_t flags,
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pwm_capture_callback_handler_t cb, void *user_data)
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{
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struct pwm_ra8_data *data = dev->data;
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if (pin != GPT_IO_PIN_GTIOCA) {
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LOG_ERR("Feature only support for gtioca");
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return -EINVAL;
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}
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if (!(flags & PWM_CAPTURE_TYPE_MASK)) {
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LOG_ERR("No PWWM capture type specified");
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return -EINVAL;
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}
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if ((flags & PWM_CAPTURE_TYPE_MASK) == PWM_CAPTURE_TYPE_BOTH) {
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LOG_ERR("Cannot capture both period and pulse width");
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return -ENOTSUP;
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}
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if (data->capture.is_busy) {
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LOG_ERR("Capture already active on this pin");
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return -EBUSY;
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}
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if (flags & PWM_CAPTURE_TYPE_PERIOD) {
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data->capture.is_pulse_capture = false;
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if (flags & PWM_POLARITY_INVERTED) {
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data->extend_cfg.start_source =
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(gpt_source_t)(GPT_SOURCE_GTIOCA_FALLING_WHILE_GTIOCB_LOW |
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GPT_SOURCE_GTIOCA_FALLING_WHILE_GTIOCB_HIGH |
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GPT_SOURCE_NONE);
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data->extend_cfg.capture_a_source = data->extend_cfg.start_source;
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} else {
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data->extend_cfg.start_source =
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(gpt_source_t)(GPT_SOURCE_GTIOCA_RISING_WHILE_GTIOCB_LOW |
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GPT_SOURCE_GTIOCA_RISING_WHILE_GTIOCB_HIGH |
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GPT_SOURCE_NONE);
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data->extend_cfg.capture_a_source = data->extend_cfg.start_source;
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}
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} else {
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data->capture.is_pulse_capture = true;
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if (flags & PWM_POLARITY_INVERTED) {
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data->extend_cfg.start_source =
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(gpt_source_t)(GPT_SOURCE_GTIOCA_FALLING_WHILE_GTIOCB_LOW |
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GPT_SOURCE_GTIOCA_FALLING_WHILE_GTIOCB_HIGH |
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GPT_SOURCE_NONE);
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data->extend_cfg.capture_a_source =
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(gpt_source_t)(GPT_SOURCE_GTIOCA_RISING_WHILE_GTIOCB_LOW |
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GPT_SOURCE_GTIOCA_RISING_WHILE_GTIOCB_HIGH |
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GPT_SOURCE_NONE);
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} else {
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data->extend_cfg.start_source =
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(gpt_source_t)(GPT_SOURCE_GTIOCA_RISING_WHILE_GTIOCB_LOW |
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GPT_SOURCE_GTIOCA_RISING_WHILE_GTIOCB_HIGH |
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GPT_SOURCE_NONE);
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data->extend_cfg.capture_a_source =
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(gpt_source_t)(GPT_SOURCE_GTIOCA_FALLING_WHILE_GTIOCB_LOW |
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GPT_SOURCE_GTIOCA_FALLING_WHILE_GTIOCB_HIGH |
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GPT_SOURCE_NONE);
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}
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}
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data->capture.callback = cb;
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data->capture.user_data = user_data;
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data->capture.continuous = flags & PWM_CAPTURE_MODE_CONTINUOUS;
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if (data->capture.continuous) {
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data->extend_cfg.stop_source = data->extend_cfg.capture_a_source;
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data->extend_cfg.clear_source = data->extend_cfg.start_source;
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} else {
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data->extend_cfg.stop_source = (gpt_source_t)(GPT_SOURCE_NONE);
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data->extend_cfg.clear_source = (gpt_source_t)(GPT_SOURCE_NONE);
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}
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return 0;
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}
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static int pwm_ra8_enable_capture(const struct device *dev, uint32_t pin)
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{
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struct pwm_ra8_data *data = dev->data;
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fsp_err_t err;
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if (pin != GPT_IO_PIN_GTIOCA) {
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LOG_ERR("Feature only support for gtioca");
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return -EINVAL;
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}
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if (data->capture.is_busy) {
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LOG_ERR("Capture already active on this pin");
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return -EBUSY;
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}
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if (!data->capture.callback) {
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LOG_ERR("PWM capture not configured");
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return -EINVAL;
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}
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data->capture.is_busy = true;
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/* Enable capture source */
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err = R_GPT_Enable(&data->fsp_ctrl);
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if (err != FSP_SUCCESS) {
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return -EIO;
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}
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/* Enable interruption */
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enable_irq(data->fsp_cfg.cycle_end_irq, data->fsp_cfg.cycle_end_irq, &data->fsp_ctrl);
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enable_irq(data->extend_cfg.capture_a_irq, data->extend_cfg.capture_a_ipl, &data->fsp_ctrl);
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R_ICU->IELSR[data->fsp_cfg.cycle_end_irq] = (elc_event_t)data->overflow_event;
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R_ICU->IELSR[data->extend_cfg.capture_a_irq] = (elc_event_t)data->capture_a_event;
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return 0;
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}
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static int pwm_ra8_disable_capture(const struct device *dev, uint32_t pin)
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{
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struct pwm_ra8_data *data = dev->data;
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fsp_err_t err;
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if (pin != GPT_IO_PIN_GTIOCA) {
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LOG_ERR("Feature only support for gtioca");
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return -EINVAL;
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}
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data->capture.is_busy = false;
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/* Disable interruption */
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disable_irq(data->fsp_cfg.cycle_end_irq);
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disable_irq(data->extend_cfg.capture_a_irq);
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R_ICU->IELSR[data->fsp_cfg.cycle_end_irq] = (elc_event_t)ELC_EVENT_NONE;
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R_ICU->IELSR[data->extend_cfg.capture_a_irq] = (elc_event_t)ELC_EVENT_NONE;
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/* Disable capture source */
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err = R_GPT_Disable(&data->fsp_ctrl);
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if (err != FSP_SUCCESS) {
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return -EIO;
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}
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/* Stop timer */
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err = R_GPT_Stop(&data->fsp_ctrl);
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if (err != FSP_SUCCESS) {
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return -EIO;
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}
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/* Clear timer */
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err = R_GPT_Reset(&data->fsp_ctrl);
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if (err != FSP_SUCCESS) {
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return -EIO;
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}
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return 0;
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}
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static void fsp_callback(timer_callback_args_t *p_args)
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{
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const struct device *dev = p_args->p_context;
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struct pwm_ra8_data *data = dev->data;
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timer_info_t info;
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(void)R_GPT_InfoGet(&data->fsp_ctrl, &info);
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uint64_t period = info.period_counts;
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/* The maximum period is one more than the maximum 16,32-bit number, but will be reflected
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* as 0
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*/
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if (period == 0U) {
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if (data->fsp_ctrl.variant == TIMER_VARIANT_16_BIT) {
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period = UINT16_MAX + 1U;
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} else {
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period = UINT32_MAX + 1U;
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}
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}
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/* Capture event */
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if (p_args->event == TIMER_EVENT_CAPTURE_A) {
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if (p_args->capture != 0U) {
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if (data->capture.is_pulse_capture == true) {
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data->capture.pulse =
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(data->capture.overflows * period) + p_args->capture;
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data->capture.callback(dev, GPT_IO_PIN_GTIOCA, 0,
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data->capture.pulse, 0,
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data->capture.user_data);
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} else {
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data->capture.period =
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(data->capture.overflows * period) + p_args->capture;
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data->capture.callback(dev, GPT_IO_PIN_GTIOCA, data->capture.period,
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0, 0, data->capture.user_data);
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}
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data->capture.overflows = 0U;
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/* Disable capture in single mode */
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if (data->capture.continuous == false) {
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pwm_ra8_disable_capture(dev, GPT_IO_PIN_GTIOCA);
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}
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}
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} else if (p_args->event == TIMER_EVENT_CYCLE_END) {
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data->capture.overflows++;
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} else {
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data->capture.callback(dev, GPT_IO_PIN_GTIOCA, 0, 0, -ECANCELED,
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data->capture.user_data);
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}
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}
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#endif /* CONFIG_PWM_CAPTURE */
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static const struct pwm_driver_api pwm_ra8_driver_api = {
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.get_cycles_per_sec = pwm_ra8_get_cycles_per_sec,
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.set_cycles = pwm_ra8_set_cycles,
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#ifdef CONFIG_PWM_CAPTURE
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.configure_capture = pwm_ra8_configure_capture,
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.enable_capture = pwm_ra8_enable_capture,
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.disable_capture = pwm_ra8_disable_capture,
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#endif /* CONFIG_PWM_CAPTURE */
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};
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static int pwm_ra8_init(const struct device *dev)
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{
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struct pwm_ra8_data *data = dev->data;
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const struct pwm_ra8_config *cfg = dev->config;
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int err;
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if (!device_is_ready(cfg->clock_dev)) {
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LOG_ERR("clock control device not ready");
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return -ENODEV;
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}
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err = clock_control_on(cfg->clock_dev, (clock_control_subsys_t)&cfg->clock_subsys);
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if (err < 0) {
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LOG_ERR("Could not initialize clock (%d)", err);
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return err;
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}
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err = pinctrl_apply_state(cfg->pincfg, PINCTRL_STATE_DEFAULT);
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if (err) {
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|
LOG_ERR("Failed to configure pins for PWM (%d)", err);
|
|
return err;
|
|
}
|
|
|
|
#if defined(CONFIG_PWM_CAPTURE)
|
|
data->fsp_cfg.p_callback = fsp_callback;
|
|
data->fsp_cfg.p_context = dev;
|
|
#endif /* defined(CONFIG_PWM_CAPTURE) */
|
|
|
|
data->fsp_cfg.p_extend = &data->extend_cfg;
|
|
|
|
err = R_GPT_Open(&data->fsp_ctrl, &data->fsp_cfg);
|
|
if (err != FSP_SUCCESS) {
|
|
return -EIO;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
#define _ELC_EVENT_GPT_CAPTURE_COMPARE_A(channel) ELC_EVENT_GPT##channel##_CAPTURE_COMPARE_A
|
|
#define _ELC_EVENT_GPT_COUNTER_OVERFLOW(channel) ELC_EVENT_GPT##channel##_COUNTER_OVERFLOW
|
|
|
|
#define ELC_EVENT_GPT_CAPTURE_COMPARE_A(channel) _ELC_EVENT_GPT_CAPTURE_COMPARE_A(channel)
|
|
#define ELC_EVENT_GPT_COUNTER_OVERFLOW(channel) _ELC_EVENT_GPT_COUNTER_OVERFLOW(channel)
|
|
|
|
#ifdef CONFIG_PWM_CAPTURE
|
|
#define PWM_RA_IRQ_CONFIG_INIT(index) \
|
|
do { \
|
|
\
|
|
IRQ_CONNECT(DT_INST_IRQ_BY_NAME(index, gtioca, irq), \
|
|
DT_INST_IRQ_BY_NAME(index, gtioca, priority), \
|
|
gpt_capture_compare_a_isr, NULL, 0); \
|
|
IRQ_CONNECT(DT_INST_IRQ_BY_NAME(index, overflow, irq), \
|
|
DT_INST_IRQ_BY_NAME(index, overflow, priority), \
|
|
gpt_counter_overflow_isr, NULL, 0); \
|
|
} while (0)
|
|
|
|
#else
|
|
#define PWM_RA_IRQ_CONFIG_INIT(index)
|
|
#endif /* CONFIG_PWM_CAPTURE */
|
|
|
|
#define PWM_RA8_INIT(index) \
|
|
PINCTRL_DT_INST_DEFINE(index); \
|
|
static const gpt_extended_cfg_t g_timer1_extend_##index = { \
|
|
.gtioca = \
|
|
{ \
|
|
.output_enabled = false, \
|
|
.stop_level = GPT_PIN_LEVEL_LOW, \
|
|
}, \
|
|
.gtiocb = \
|
|
{ \
|
|
.output_enabled = false, \
|
|
.stop_level = GPT_PIN_LEVEL_LOW, \
|
|
}, \
|
|
.start_source = (gpt_source_t)(GPT_SOURCE_NONE), \
|
|
.stop_source = (gpt_source_t)(GPT_SOURCE_NONE), \
|
|
.clear_source = (gpt_source_t)(GPT_SOURCE_NONE), \
|
|
.count_up_source = (gpt_source_t)(GPT_SOURCE_NONE), \
|
|
.count_down_source = (gpt_source_t)(GPT_SOURCE_NONE), \
|
|
.capture_a_source = (gpt_source_t)(GPT_SOURCE_NONE), \
|
|
.capture_b_source = (gpt_source_t)(GPT_SOURCE_NONE), \
|
|
.capture_a_ipl = DT_INST_IRQ_BY_NAME(index, gtioca, priority), \
|
|
.capture_b_ipl = BSP_IRQ_DISABLED, \
|
|
.capture_a_irq = DT_INST_IRQ_BY_NAME(index, gtioca, irq), \
|
|
.capture_b_irq = FSP_INVALID_VECTOR, \
|
|
.capture_filter_gtioca = GPT_CAPTURE_FILTER_NONE, \
|
|
.capture_filter_gtiocb = GPT_CAPTURE_FILTER_NONE, \
|
|
.p_pwm_cfg = NULL, \
|
|
.gtior_setting.gtior = (0x0U), \
|
|
}; \
|
|
static struct pwm_ra8_data pwm_ra8_data_##index = { \
|
|
.fsp_cfg = \
|
|
{ \
|
|
.mode = TIMER_MODE_PWM, \
|
|
.source_div = DT_INST_PROP(index, divider), \
|
|
.channel = DT_INST_PROP(index, channel), \
|
|
.cycle_end_ipl = DT_INST_IRQ_BY_NAME(index, overflow, priority), \
|
|
.cycle_end_irq = DT_INST_IRQ_BY_NAME(index, overflow, irq), \
|
|
}, \
|
|
.extend_cfg = g_timer1_extend_##index, \
|
|
.capture_a_event = ELC_EVENT_GPT_CAPTURE_COMPARE_A(DT_INST_PROP(index, channel)), \
|
|
.overflow_event = ELC_EVENT_GPT_COUNTER_OVERFLOW(DT_INST_PROP(index, channel)), \
|
|
}; \
|
|
static const struct pwm_ra8_config pwm_ra8_config_##index = { \
|
|
.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(index), \
|
|
.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(index)), \
|
|
.clock_subsys = { \
|
|
.mstp = (uint32_t)DT_INST_CLOCKS_CELL_BY_IDX(index, 0, mstp), \
|
|
.stop_bit = DT_INST_CLOCKS_CELL_BY_IDX(index, 0, stop_bit), \
|
|
}}; \
|
|
static int pwm_ra8_init_##index(const struct device *dev) \
|
|
{ \
|
|
PWM_RA_IRQ_CONFIG_INIT(index); \
|
|
int err = pwm_ra8_init(dev); \
|
|
if (err != 0) { \
|
|
return err; \
|
|
} \
|
|
return 0; \
|
|
} \
|
|
DEVICE_DT_INST_DEFINE(index, pwm_ra8_init_##index, NULL, &pwm_ra8_data_##index, \
|
|
&pwm_ra8_config_##index, POST_KERNEL, CONFIG_PWM_INIT_PRIORITY, \
|
|
&pwm_ra8_driver_api);
|
|
|
|
DT_INST_FOREACH_STATUS_OKAY(PWM_RA8_INIT);
|