373 lines
9.9 KiB
C
373 lines
9.9 KiB
C
/*
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* Copyright (c) 2016 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <errno.h>
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#include <device.h>
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#include <i2c.h>
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#include <board.h>
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#include "qm_ss_i2c.h"
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#include "qm_ss_isr.h"
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#include "ss_clk.h"
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#include "i2c-priv.h"
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/* Convenient macros to get the controller instance and the driver data. */
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#define GET_CONTROLLER_INSTANCE(dev) \
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(((const struct i2c_qmsi_ss_config_info *) \
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dev->config->config_info)->instance)
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#define GET_DRIVER_DATA(dev) \
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((struct i2c_qmsi_ss_driver_data *)dev->driver_data)
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struct i2c_qmsi_ss_config_info {
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qm_ss_i2c_t instance; /* Controller instance. */
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u32_t bitrate;
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void (*irq_cfg)(void);
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};
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struct i2c_qmsi_ss_driver_data {
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struct k_sem device_sync_sem;
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int transfer_status;
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struct k_sem sem;
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#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
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u32_t device_power_state;
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qm_ss_i2c_context_t i2c_ctx;
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#endif
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};
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#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
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static void ss_i2c_qmsi_set_power_state(struct device *dev,
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u32_t power_state)
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{
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struct i2c_qmsi_ss_driver_data *drv_data = GET_DRIVER_DATA(dev);
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drv_data->device_power_state = power_state;
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}
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static u32_t ss_i2c_qmsi_get_power_state(struct device *dev)
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{
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struct i2c_qmsi_ss_driver_data *drv_data = GET_DRIVER_DATA(dev);
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return drv_data->device_power_state;
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}
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static int ss_i2c_suspend_device(struct device *dev)
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{
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if (device_busy_check(dev)) {
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return -EBUSY;
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}
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struct i2c_qmsi_ss_driver_data *drv_data = GET_DRIVER_DATA(dev);
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qm_ss_i2c_save_context(GET_CONTROLLER_INSTANCE(dev),
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&drv_data->i2c_ctx);
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ss_i2c_qmsi_set_power_state(dev, DEVICE_PM_SUSPEND_STATE);
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return 0;
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}
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static int ss_i2c_resume_device_from_suspend(struct device *dev)
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{
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struct i2c_qmsi_ss_driver_data *drv_data = GET_DRIVER_DATA(dev);
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qm_ss_i2c_restore_context(GET_CONTROLLER_INSTANCE(dev),
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&drv_data->i2c_ctx);
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ss_i2c_qmsi_set_power_state(dev, DEVICE_PM_ACTIVE_STATE);
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return 0;
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}
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/*
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* Implements the driver control management functionality
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* the *context may include IN data or/and OUT data
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*/
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static int ss_i2c_device_ctrl(struct device *dev, u32_t ctrl_command,
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void *context)
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{
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if (ctrl_command == DEVICE_PM_SET_POWER_STATE) {
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if (*((u32_t *)context) == DEVICE_PM_SUSPEND_STATE) {
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return ss_i2c_suspend_device(dev);
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} else if (*((u32_t *)context) == DEVICE_PM_ACTIVE_STATE) {
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return ss_i2c_resume_device_from_suspend(dev);
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}
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} else if (ctrl_command == DEVICE_PM_GET_POWER_STATE) {
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*((u32_t *)context) = ss_i2c_qmsi_get_power_state(dev);
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}
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return 0;
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}
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#else
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#define ss_i2c_qmsi_set_power_state(...)
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#endif /* CONFIG_DEVICE_POWER_MANAGEMENT */
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static int i2c_qmsi_ss_init(struct device *dev);
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#ifdef CONFIG_I2C_SS_0
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static struct i2c_qmsi_ss_driver_data driver_data_0;
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static void i2c_qmsi_ss_config_irq_0(void);
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static const struct i2c_qmsi_ss_config_info config_info_0 = {
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.instance = QM_SS_I2C_0,
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.bitrate = CONFIG_I2C_SS_0_BITRATE,
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.irq_cfg = i2c_qmsi_ss_config_irq_0,
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};
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DEVICE_DEFINE(i2c_ss_0, CONFIG_I2C_SS_0_NAME, i2c_qmsi_ss_init,
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ss_i2c_device_ctrl, &driver_data_0, &config_info_0, POST_KERNEL,
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE, NULL);
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static void i2c_qmsi_ss_config_irq_0(void)
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{
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u32_t mask = 0;
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/* Need to unmask the interrupts in System Control Subsystem (SCSS)
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* so the interrupt controller can route these interrupts to
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* the sensor subsystem.
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*/
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mask = sys_read32(SCSS_REGISTER_BASE + I2C_SS_0_ERR_MASK);
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mask &= INT_ENABLE_ARC;
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sys_write32(mask, SCSS_REGISTER_BASE + I2C_SS_0_ERR_MASK);
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mask = sys_read32(SCSS_REGISTER_BASE + I2C_SS_0_TX_MASK);
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mask &= INT_ENABLE_ARC;
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sys_write32(mask, SCSS_REGISTER_BASE + I2C_SS_0_TX_MASK);
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mask = sys_read32(SCSS_REGISTER_BASE + I2C_SS_0_RX_MASK);
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mask &= INT_ENABLE_ARC;
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sys_write32(mask, SCSS_REGISTER_BASE + I2C_SS_0_RX_MASK);
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mask = sys_read32(SCSS_REGISTER_BASE + I2C_SS_0_STOP_MASK);
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mask &= INT_ENABLE_ARC;
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sys_write32(mask, SCSS_REGISTER_BASE + I2C_SS_0_STOP_MASK);
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/* Connect the IRQs to ISR */
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IRQ_CONNECT(CONFIG_I2C_SS_0_ERR_IRQ, CONFIG_I2C_SS_0_ERR_IRQ_PRI,
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qm_ss_i2c_0_error_isr, DEVICE_GET(i2c_ss_0), 0);
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IRQ_CONNECT(CONFIG_I2C_SS_0_RX_IRQ, CONFIG_I2C_SS_0_RX_IRQ_PRI,
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qm_ss_i2c_0_rx_avail_isr, DEVICE_GET(i2c_ss_0), 0);
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IRQ_CONNECT(CONFIG_I2C_SS_0_TX_IRQ, CONFIG_I2C_SS_0_TX_IRQ_PRI,
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qm_ss_i2c_0_tx_req_isr, DEVICE_GET(i2c_ss_0), 0);
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IRQ_CONNECT(CONFIG_I2C_SS_0_STOP_IRQ, CONFIG_I2C_SS_0_STOP_IRQ_PRI,
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qm_ss_i2c_0_stop_det_isr, DEVICE_GET(i2c_ss_0), 0);
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irq_enable(CONFIG_I2C_SS_0_ERR_IRQ);
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irq_enable(CONFIG_I2C_SS_0_RX_IRQ);
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irq_enable(CONFIG_I2C_SS_0_TX_IRQ);
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irq_enable(CONFIG_I2C_SS_0_STOP_IRQ);
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}
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#endif /* CONFIG_I2C_SS_0 */
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#ifdef CONFIG_I2C_SS_1
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static struct i2c_qmsi_ss_driver_data driver_data_1;
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static void i2c_qmsi_ss_config_irq_1(void);
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static const struct i2c_qmsi_ss_config_info config_info_1 = {
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.instance = QM_SS_I2C_1,
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.bitrate = CONFIG_I2C_SS_1_BITRATE,
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.irq_cfg = i2c_qmsi_ss_config_irq_1,
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};
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DEVICE_DEFINE(i2c_ss_1, CONFIG_I2C_SS_1_NAME, i2c_qmsi_ss_init,
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ss_i2c_device_ctrl, &driver_data_1, &config_info_1, POST_KERNEL,
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE, NULL);
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static void i2c_qmsi_ss_config_irq_1(void)
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{
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u32_t mask = 0;
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/* Need to unmask the interrupts in System Control Subsystem (SCSS)
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* so the interrupt controller can route these interrupts to
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* the sensor subsystem.
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*/
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mask = sys_read32(SCSS_REGISTER_BASE + I2C_SS_1_ERR_MASK);
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mask &= INT_ENABLE_ARC;
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sys_write32(mask, SCSS_REGISTER_BASE + I2C_SS_1_ERR_MASK);
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mask = sys_read32(SCSS_REGISTER_BASE + I2C_SS_1_TX_MASK);
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mask &= INT_ENABLE_ARC;
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sys_write32(mask, SCSS_REGISTER_BASE + I2C_SS_1_TX_MASK);
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mask = sys_read32(SCSS_REGISTER_BASE + I2C_SS_1_RX_MASK);
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mask &= INT_ENABLE_ARC;
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sys_write32(mask, SCSS_REGISTER_BASE + I2C_SS_1_RX_MASK);
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mask = sys_read32(SCSS_REGISTER_BASE + I2C_SS_1_STOP_MASK);
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mask &= INT_ENABLE_ARC;
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sys_write32(mask, SCSS_REGISTER_BASE + I2C_SS_1_STOP_MASK);
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/* Connect the IRQs to ISR */
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IRQ_CONNECT(CONFIG_I2C_SS_1_ERR_IRQ, CONFIG_I2C_SS_1_ERR_IRQ_PRI,
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qm_ss_i2c_1_error_isr, DEVICE_GET(i2c_ss_1), 0);
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IRQ_CONNECT(CONFIG_I2C_SS_1_RX_IRQ, CONFIG_I2C_SS_1_RX_IRQ_PRI,
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qm_ss_i2c_1_rx_avail_isr, DEVICE_GET(i2c_ss_1), 0);
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IRQ_CONNECT(CONFIG_I2C_SS_1_TX_IRQ, CONFIG_I2C_SS_1_TX_IRQ_PRI,
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qm_ss_i2c_1_tx_req_isr, DEVICE_GET(i2c_ss_1), 0);
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IRQ_CONNECT(CONFIG_I2C_SS_1_STOP_IRQ, CONFIG_I2C_SS_1_STOP_IRQ_PRI,
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qm_ss_i2c_1_stop_det_isr, DEVICE_GET(i2c_ss_1), 0);
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irq_enable(CONFIG_I2C_SS_1_ERR_IRQ);
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irq_enable(CONFIG_I2C_SS_1_RX_IRQ);
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irq_enable(CONFIG_I2C_SS_1_TX_IRQ);
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irq_enable(CONFIG_I2C_SS_1_STOP_IRQ);
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}
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#endif /* CONFIG_I2C_SS_1 */
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static int i2c_qmsi_ss_configure(struct device *dev, u32_t config)
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{
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qm_ss_i2c_t instance = GET_CONTROLLER_INSTANCE(dev);
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struct i2c_qmsi_ss_driver_data *driver_data = GET_DRIVER_DATA(dev);
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qm_ss_i2c_config_t qm_cfg;
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u32_t i2c_base = QM_SS_I2C_0_BASE;
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/* This driver only supports master mode. */
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if (!(I2C_MODE_MASTER & config)) {
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return -EINVAL;
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}
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if (I2C_ADDR_10_BITS & config) {
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qm_cfg.address_mode = QM_SS_I2C_10_BIT;
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} else {
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qm_cfg.address_mode = QM_SS_I2C_7_BIT;
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}
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switch (I2C_SPEED_GET(config)) {
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case I2C_SPEED_STANDARD:
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qm_cfg.speed = QM_SS_I2C_SPEED_STD;
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break;
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case I2C_SPEED_FAST:
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qm_cfg.speed = QM_SS_I2C_SPEED_FAST;
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break;
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default:
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return -EINVAL;
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}
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k_sem_take(&driver_data->sem, K_FOREVER);
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if (qm_ss_i2c_set_config(instance, &qm_cfg) != 0) {
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k_sem_give(&driver_data->sem);
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return -EIO;
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}
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k_sem_give(&driver_data->sem);
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if (instance == QM_SS_I2C_1) {
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i2c_base = QM_SS_I2C_1_BASE;
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}
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__builtin_arc_sr(((CONFIG_I2C_SS_SDA_SETUP << 16) +
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CONFIG_I2C_SS_SDA_HOLD),
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(i2c_base + QM_SS_I2C_SDA_CONFIG));
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return 0;
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}
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static void transfer_complete(void *data, int rc, qm_ss_i2c_status_t status,
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uint32_t len)
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{
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struct device *dev = data;
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struct i2c_qmsi_ss_driver_data *driver_data;
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ARG_UNUSED(status);
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ARG_UNUSED(len);
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driver_data = GET_DRIVER_DATA(dev);
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driver_data->transfer_status = rc;
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k_sem_give(&driver_data->device_sync_sem);
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}
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static int i2c_qmsi_ss_transfer(struct device *dev, struct i2c_msg *msgs,
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u8_t num_msgs, u16_t addr)
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{
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struct i2c_qmsi_ss_driver_data *driver_data = GET_DRIVER_DATA(dev);
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qm_ss_i2c_t instance = GET_CONTROLLER_INSTANCE(dev);
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int rc;
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__ASSERT_NO_MSG(msgs);
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if (!num_msgs) {
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return 0;
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}
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device_busy_set(dev);
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for (int i = 0; i < num_msgs; i++) {
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u8_t *buf = msgs[i].buf;
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u32_t len = msgs[i].len;
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u8_t op = msgs[i].flags & I2C_MSG_RW_MASK;
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bool stop = (msgs[i].flags & I2C_MSG_STOP) == I2C_MSG_STOP;
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qm_ss_i2c_transfer_t xfer = { 0 };
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if (op == I2C_MSG_WRITE) {
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xfer.tx = buf;
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xfer.tx_len = len;
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} else {
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xfer.rx = buf;
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xfer.rx_len = len;
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}
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xfer.callback = transfer_complete;
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xfer.callback_data = dev;
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xfer.stop = stop;
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k_sem_take(&driver_data->sem, K_FOREVER);
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rc = qm_ss_i2c_master_irq_transfer(instance, &xfer, addr);
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k_sem_give(&driver_data->sem);
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if (rc != 0) {
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device_busy_clear(dev);
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return -EIO;
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}
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/* Block current thread until the I2C transfer completes. */
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k_sem_take(&driver_data->device_sync_sem, K_FOREVER);
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if (driver_data->transfer_status != 0) {
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device_busy_clear(dev);
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return -EIO;
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}
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}
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device_busy_clear(dev);
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return 0;
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}
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static const struct i2c_driver_api api = {
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.configure = i2c_qmsi_ss_configure,
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.transfer = i2c_qmsi_ss_transfer,
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};
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static int i2c_qmsi_ss_init(struct device *dev)
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{
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struct i2c_qmsi_ss_driver_data *driver_data = GET_DRIVER_DATA(dev);
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const struct i2c_qmsi_ss_config_info *config = dev->config->config_info;
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qm_ss_i2c_t instance = GET_CONTROLLER_INSTANCE(dev);
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u32_t bitrate_cfg;
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int err;
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config->irq_cfg();
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ss_clk_i2c_enable(instance);
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k_sem_init(&driver_data->sem, 1, UINT_MAX);
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bitrate_cfg = _i2c_map_dt_bitrate(config->bitrate);
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err = i2c_qmsi_ss_configure(dev, I2C_MODE_MASTER | bitrate_cfg);
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if (err < 0) {
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return err;
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}
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k_sem_init(&driver_data->device_sync_sem, 0, UINT_MAX);
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dev->driver_api = &api;
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ss_i2c_qmsi_set_power_state(dev, DEVICE_PM_ACTIVE_STATE);
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return 0;
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}
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