Now that dts i2 qmsi ss nodes generate the right options, let's use
them. Apply the relevant fixup on the targeted SoC.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Cleanup I2C drivers to not use bitfield access for config information
and instead use accessor macros that use shifts & masks. This is
cleanup towards removing the bitfield access in the future.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Change the common "init with 0" + "give" idiom to "init with 1". This
won't change the behavior or performance, but should decrease the size
ever so slightly.
This change has been performed mechanically with the following
Coccinelle script:
@@
expression SEM;
expression LIMIT;
expression TIMEOUT;
@@
- k_sem_init(SEM, 0, LIMIT);
- k_sem_give(SEM);
+ k_sem_init(SEM, 1, LIMIT);
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99
integer types. This handles the remaining includes and kernel, plus
touching up various points that we skipped because of include
dependancies. We also convert the PRI printf formatters in the arch
code over to normal formatters.
Jira: ZEP-2051
Change-Id: Iecbb12601a3ee4ea936fd7ddea37788a645b08b0
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99
integer types.
Jira: ZEP-2051
Change-Id: I08f51e2bfd475f6245771c1bd2df7ffc744c48c4
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit removes unnecessary CONFIG_SYS_POWER_DEEP_SLEEP protection
in shim drivers as QMSI 1.4 has introduced empty context save/restore
functions that can be called in Quark D2000, therefore keeping common
code at the shim driver level for Quark SE and D2000.
Change-Id: Ia2a466327f999668c6511c0193014e9151bff6ae
Signed-off-by: Juan Solano <juanx.solano.menacho@intel.com>
Update the builtin QMSI code to 1.4 (RC2).
The below shim drivers were updated for API or interface changes:
- aio
- counter
- i2c_ss
- rtc
- wdt.
Also, arch soc specific power management code were updated.
Jira: ZEP-1572
Change-Id: Ibc8fae032a39ffb2c2c997f697835bc0208fd308
Signed-off-by: Jesus Sanchez-Palencia <jesus.sanchez-palencia@intel.com>
Signed-off-by: Kuo-Lang Tseng <kuo-lang.tseng@intel.com>
The I2C drivers handle an empty list of I2C messages inconsistenty.
There are two different behaviours, one set of drivers dectects a
requests to transfer zero messages and return -EINVAL while the other
group simple transfer no data and return success.
Adopt the latter behaviour consistently across all drivers. Update
the i2c.h API documentation to reflect this behaviour.
Change-Id: I427fc1b0e18ddc04b7b59c294e0240b3d6ca4073
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
Replace the existing Apache 2.0 boilerplate header with an SPDX tag
throughout the zephyr code tree. This patch was generated via a
script run over the master branch.
Also updated doc/porting/application.rst that had a dependency on
line numbers in a literal include.
Manually updated subsys/logging/sys_log.c that had a malformed
header in the original file. Also cleanup several cases that already
had a SPDX tag and we either got a duplicate or missed updating.
Jira: ZEP-1457
Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
When CONFIG_SYS_POWER_DEEP_SLEEP is enabled, i2c_qmsi_ss will
keep entering deep sleep because it needs to wait until the
current transfer completes, which blocks the current thread.
The system keeps entering deep sleep again and again and the
transfer will never complete.
Add device_busy_set() to i2c_qmsi_ss driver to indicate that
the device is busy and block the system from entering deep
sleep during transaction.
Jira: ZEP-1487
Change-Id: Ia681d242349bce5a9867e54df4e65dba09005930
Signed-off-by: Qiu Peiyang <peiyangx.qiu@intel.com>
Enable arc to access the i2c controller on I/O fabric.
There are two i2c controllers on quark se SoC. One is attached
to the I/O fabric and the other one is in the sensor system.
X86 cpu is only able to access the i2c controller on the I/O
fabric and the access is supported by existing code. HW allows
arc to access both controllers. But, the existing code only
gives arc access to the controller in the sensor sub-system.
Let's grant arc the access to the controller on I/O fabric as
well by the following changes.
1. Add i2c_qmsi.c into arc compilation.
2. Use the already defined macros to choose interrupt numbers
and do interrupt unmasking automatically based on the
compilation targets.
3. Add new symbols in Kconfig including driver names for both
controllers
Jira: ZEP-1189
Change-Id: I317da6038c50e0c8bd16f446182c1f8bdf6d3ba2
Signed-off-by: Baohong Liu <baohong.liu@intel.com>
Device sync APIs are actually wrappers for semaphores.
Let's replace them with semaphores.
Jira: ZEP-1411
Change-Id: I5662057222aec54f02db9d9cdcd7f4f006c6c530
Signed-off-by: Baohong Liu <baohong.liu@intel.com>
This commit updates the i2c_qmsi_ss driver by adding save/restore
context functionality for power management, using the corresponsing
QMSI APIs.
Jira: ZEP-666
Change-Id: I36fb18b52edd4dac4c4b6cb98162adbca74800cb
Signed-off-by: JuanX Solano Menacho <juanx.solano.menacho@intel.com>
PRIMARY, SECONDARY, NANOKERNEL, MICROKERNEL init levels are now
deprecated.
New init levels introduced: PRE_KERNEL_1, PRE_KERNEL_2, POST_KERNEL
to replace them.
Most existing code has instances of PRIMARY replaced with PRE_KERNEL_1,
SECONDARY with POST_KERNEL as SECONDARY has had a longstanding bug
where the documentation specified SECONDARY ran before the kernel started
up, but actually ran afterwards.
Change-Id: I771bc634e9caf7f17dbf214a270bc9967eed7d32
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Update the QMSI drop we maintain in Zephyr, and fix the build where
needed:
- QM_SCSS_INT is renamed to QM_INTERRUPT_ROUTER;
- every member of QM_INTERRUPT_ROUTER was renamed as well;
- QM_IRQ_* renamed too, mostly added _INT at the end;
- some isr functions were renamed to keep their names consistent;
- build for x86 needs to define QM_LAKEMONT, as QM_SENSOR was for ARC.
Change-Id: I459029ca0d373f6c831e2bb8ebd52402a55994d1
Signed-off-by: Iván Briano <ivan.briano@intel.com>
Change the signal ramp up/down config parameters in i2c driver
module to SoC specific.
Jira: ZEP-753
Change-Id: Ie01f1d890a7133d30ea53eee07f60354734a8571
Signed-off-by: Baohong Liu <baohong.liu@intel.com>
Fix i2c failure while multiple slaves are connected to the
same i2c interface. Higher load on the i2c bus makes i2c
signal less nice. The requirement for signal ramp up and
ramp down time needs to be loosened.
Jira: ZEP-646
Change-Id: If698d7ba741788857694f166ecc602c2a94cb12e
Signed-off-by: Baohong Liu <baohong.liu@intel.com>
Drivers that implement power management should use the preferred
device_pm_ops method instead.
Change-Id: I9ae06e26b77325265bbe46bdee82ba39dedb6b79
Signed-off-by: Iván Briano <ivan.briano@intel.com>
The idle status check before a i2c transfer is not a reliable
way to check whether i2c master is ready to transfer data. If
the data transfer for the previous API call is done, but, a
stop condition is not sent by the previous API, the i2c master
is not idle, but, it can start new data transfer.
Change-Id: I93dbf46cef6272f3da69a0d67fb737c9b480791f
Signed-off-by: Baohong Liu <baohong.liu@intel.com>
Fix a bug in i2c_qmsi_transfer function in the shim driver.
The function did not wait for the completion of a msg transfer
before starting another msg transfer. Similar issue exists in
the i2c sensor shim driver. It is also fixed.
Change-Id: I1f8ad2281fa185d85db25a4682ed596c02ea322e
Signed-off-by: Baohong Liu <baohong.liu@intel.com>
This will allow the driver to be safe from fibers and task
Jira: ZEP-411
Change-Id: I714f22c8df7002c45bed981c493e11af91c70d93
Signed-off-by: Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
Add I2C QMSI shim driver for sensor system based on QMSI 1.1
Origin: Original
Change-Id: I9c8efe49e8e9b7a5f8496fa49beb68e409148be7
Signed-off-by: Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Tomasz Bursztyka