Leandro Pereira a71c365180 arch: xtensa: Reduce size of interrupt handling routines ... This patch reduces the size of ISRs by changing the script to generate the dispatcher per level to, instead of generating an indirect call per mask match, do that just once at the function end. For ESP32, this provides ~380bytes of savings in a (very) hot path (text, just for the matcher functions generated by xtensa_intgen.py, drop from 2197 bytes to 1817 bytes). The generated code also uses the BIT() macro, which shifts 1UL instead of 1. Shifting a signed integer is UB in C. Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>		2018-10-22 13:38:29 -07:00
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core	arch: xtensa: Reduce size of interrupt handling routines	2018-10-22 13:38:29 -07:00
include	xtensa: specify which SR to store pointer to _kernel.cpu struct	2018-10-19 17:52:45 -04:00
CMakeLists.txt	xtensa: move soc to top-level dir soc/	2018-09-13 00:56:48 -04:00
Kconfig	xtensa: specify which SR to store pointer to _kernel.cpu struct	2018-10-19 17:52:45 -04:00