zephyr/arch
Leandro Pereira a71c365180 arch: xtensa: Reduce size of interrupt handling routines
This patch reduces the size of ISRs by changing the script to generate
the dispatcher per level to, instead of generating an indirect call per
mask match, do that just once at the function end.

For ESP32, this provides ~380bytes of savings in a (very) hot path
(text, just for the matcher functions generated by xtensa_intgen.py,
drop from 2197 bytes to 1817 bytes).

The generated code also uses the BIT() macro, which shifts 1UL instead
of 1.  Shifting a signed integer is UB in C.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2018-10-22 13:38:29 -07:00
..
arc sys_clock: Fix unsafe tick count usage 2018-10-16 15:03:10 -04:00
arm arch: arm: exc.h: MISRA C violation fix in _IsInIsr 2018-10-17 12:17:58 -04:00
common tests: benchmarks: timing_info: Enable benchmarks for riscv32. 2018-08-20 06:51:25 -07:00
nios2 arch: kernel_arch_func.h: Fix MISRA violation 2018-10-17 12:17:58 -04:00
posix arch: kernel_arch_func.h: Fix MISRA violation 2018-10-17 12:17:58 -04:00
riscv32 arch: kernel_arch_func.h: Fix MISRA violation 2018-10-17 12:17:58 -04:00
x86 arch: kernel_arch_func.h: Fix MISRA violation 2018-10-17 12:17:58 -04:00
xtensa arch: xtensa: Reduce size of interrupt handling routines 2018-10-22 13:38:29 -07:00
CMakeLists.txt arch: Cmake: Add __ZEPHYR_SUPERVISOR__ macro for arch files. 2018-05-15 17:48:18 +03:00
Kconfig arch: increase privileged stack with mpu stack guard 2018-10-19 16:09:50 -04:00