29 lines
1.2 KiB
Tcl
29 lines
1.2 KiB
Tcl
#**************************************************************
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# Create Clock
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#**************************************************************
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derive_pll_clocks
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# JTAG Signal Constraints constrain the TCK port, assuming a 10MHz JTAG clock and 3ns delays
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create_clock -name {altera_reserved_tck} -period 41.667 [get_ports { altera_reserved_tck }]
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set_input_delay -clock altera_reserved_tck -clock_fall -max 5 [get_ports altera_reserved_tdi]
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set_input_delay -clock altera_reserved_tck -clock_fall -max 5 [get_ports altera_reserved_tms]
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set_output_delay -clock altera_reserved_tck 5 [get_ports altera_reserved_tdo]
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create_clock -name {clk_50} -period 20.000 {clk_50}
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set_false_path -to [get_ports {user_led[*]}]
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set_false_path -to [get_ports {fpga_reset_n}]
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set_false_path -from [get_ports {fpga_reset_n}]
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derive_clock_uncertainty
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# QSPI interface
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set_output_delay -clock {clk_50 } -rise -min 11 [get_ports {qspi_io[*]}]
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set_output_delay -clock {clk_50 } -rise -min 11 [get_ports {qspi_clk}]
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set_output_delay -clock {clk_50 } -rise -min 11 [get_ports {qspi_csn}]
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set_input_delay -clock {clk_50 } -rise -min 10 [get_ports {qspi_io[*]}]
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# UART
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set_false_path -from * -to [get_ports {uart_tx}]
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