zephyr/dts/riscv
Filip Kokosinski ecf308e8de dts/andes: adjust the sizes of PLIC nodes
This commit adjusts the sizes of the two PLIC nodes AE350 defines:
* `plic0` size is changed from `0x04000000` to `0x02000000`
* `plic_sw` size is changed from `0x04000000` to `0x00400000`

Without these change, `plic0` address space would overlap with `plic_sw`,
and with other memory-mapped peripherals.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2024-10-31 14:17:02 -05:00
..
andes dts/andes: adjust the sizes of PLIC nodes 2024-10-31 14:17:02 -05:00
efinix
espressif soc: dts: esp32c3: esp8685: Add files to indicate support 2024-10-29 16:04:02 -07:00
gd
ite
lowrisc
microchip
niosv
nordic soc: nordic: Remove the nRF54L15 EngA 2024-10-21 01:46:39 +01:00
openisa
qemu
sensry
sifive
starfive
telink
neorv32.dtsi
renode_riscv32_virt.dtsi
riscv32-litex-vexriscv.dtsi