141 lines
4.0 KiB
ArmAsm
141 lines
4.0 KiB
ArmAsm
/*
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* Copyright (c) 2016 Cadence Design Systems, Inc.
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* SPDX-License-Identifier: Apache-2.0
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*/
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/******************************************************************************
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Xtensa interrupt handling data and assembly routines.
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Also see xtensa_intr.c and xtensa_vectors.S.
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******************************************************************************/
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#include <xtensa/hal.h>
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#include <xtensa/config/core.h>
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#include "xtensa_rtos.h"
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#include "xtensa_context.h"
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#if XCHAL_HAVE_INTERRUPTS
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/*
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-------------------------------------------------------------------------------
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INTENABLE virtualization information.
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-------------------------------------------------------------------------------
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*/
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.data
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.global _xt_intdata
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.align 8
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_xt_intdata:
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.global _xt_intenable
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.type _xt_intenable,@object
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.size _xt_intenable,4
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.global _xt_vpri_mask
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.type _xt_vpri_mask,@object
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.size _xt_vpri_mask,4
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_xt_intenable: .word 0 /* Virtual INTENABLE */
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_xt_vpri_mask: .word 0xFFFFFFFF /* Virtual priority mask */
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#endif /* XCHAL_HAVE_INTERRUPTS */
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#if XCHAL_HAVE_EXCEPTIONS
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/*
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-------------------------------------------------------------------------------
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Table of C-callable exception handlers for each exception. Note that not all
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slots will be active, because some exceptions (e.g. coprocessor exceptions)
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are always handled by the OS and cannot be hooked by user handlers.
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-------------------------------------------------------------------------------
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*/
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.data
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.global _xt_exception_table
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.align 4
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_xt_exception_table:
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.rept XCHAL_EXCCAUSE_NUM
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.word xt_unhandled_exception /* handler address */
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.endr
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#endif
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/*
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-------------------------------------------------------------------------------
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unsigned int _xt_ints_on ( unsigned int mask )
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Enables a set of interrupts. Does not simply set INTENABLE directly, but
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computes it as a function of the current virtual priority.
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Can be called from interrupt handlers.
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-------------------------------------------------------------------------------
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*/
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.text
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.align 4
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.global _xt_ints_on
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.type _xt_ints_on,@function
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_xt_ints_on:
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ENTRY0
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#if XCHAL_HAVE_INTERRUPTS
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movi a3, 0
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movi a4, _xt_intdata
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xsr a3, INTENABLE /* Disables all interrupts */
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rsync
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l32i a3, a4, 0 /* a3 = _xt_intenable */
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l32i a6, a4, 4 /* a6 = _xt_vpri_mask */
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or a5, a3, a2 /* a5 = _xt_intenable | mask */
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s32i a5, a4, 0 /* _xt_intenable |= mask */
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and a5, a5, a6 /* a5 = _xt_intenable & _xt_vpri_mask */
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wsr a5, INTENABLE /* Reenable interrupts */
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mov a2, a3 /* Previous mask */
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#else
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movi a2, 0 /* Return zero */
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#endif
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RET0
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.size _xt_ints_on, . - _xt_ints_on
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/*
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-------------------------------------------------------------------------------
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unsigned int _xt_ints_off ( unsigned int mask )
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Disables a set of interrupts. Does not simply set INTENABLE directly,
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but computes it as a function of the current virtual priority.
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Can be called from interrupt handlers.
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-------------------------------------------------------------------------------
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*/
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.text
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.align 4
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.global _xt_ints_off
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.type _xt_ints_off,@function
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_xt_ints_off:
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ENTRY0
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#if XCHAL_HAVE_INTERRUPTS
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movi a3, 0
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movi a4, _xt_intdata
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xsr a3, INTENABLE /* Disables all interrupts */
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rsync
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l32i a3, a4, 0 /* a3 = _xt_intenable */
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l32i a6, a4, 4 /* a6 = _xt_vpri_mask */
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or a5, a3, a2 /* a5 = _xt_intenable | mask */
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xor a5, a5, a2 /* a5 = _xt_intenable & ~mask */
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s32i a5, a4, 0 /* _xt_intenable &= ~mask */
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and a5, a5, a6 /* a5 = _xt_intenable & _xt_vpri_mask */
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wsr a5, INTENABLE /* Reenable interrupts */
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mov a2, a3 /* Previous mask */
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#else
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movi a2, 0 /* return zero */
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#endif
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RET0
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.size _xt_ints_off, . - _xt_ints_off
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