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zephyr/dts/riscv/ite/it8xxx2.dtsi

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/*
* Copyright (c) 2020 ITE Corporation. All Rights Reserved.
* Copyright (c) 2019-2020 Jyunlin Chen <jyunlin.chen@ite.com.tw>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <zephyr/dt-bindings/dt-util.h>
#include <zephyr/dt-bindings/adc/adc.h>
#include <zephyr/dt-bindings/interrupt-controller/ite-intc.h>
#include <zephyr/dt-bindings/interrupt-controller/it8xxx2-wuc.h>
#include <zephyr/dt-bindings/i2c/i2c.h>
#include <zephyr/dt-bindings/i2c/it8xxx2-i2c.h>
#include <zephyr/dt-bindings/pinctrl/it8xxx2-pinctrl.h>
#include <zephyr/dt-bindings/pwm/pwm.h>
#include <zephyr/dt-bindings/pwm/it8xxx2_pwm.h>
#include <zephyr/dt-bindings/sensor/it8xxx2_vcmp.h>
#include <zephyr/dt-bindings/sensor/it8xxx2_tach.h>
#include <zephyr/dt-bindings/gpio/gpio.h>
#include "ite/it8xxx2-wuc-map.dtsi"
/ {
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "ite,riscv-ite";
riscv,isa = "rv32imafc_zifencei";
device_type = "cpu";
reg = <0>;
cpu-power-states = <&standby>;
};
power-states {
standby: standby {
compatible = "zephyr,power-state";
power-state-name = "standby";
min-residency-us = <500>;
};
};
};
soc {
#address-cells = <1>;
#size-cells = <1>;
ranges;
bbram: bb-ram@f02200 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "ite,it8xxx2-bbram";
status = "okay";
reg = <0x00f02200 0xc0>;
};
flashctrl: flash-controller@f01000 {
compatible = "ite,it8xxx2-flash-controller";
reg = <0x00f01000 0x100>;
#address-cells = <1>;
#size-cells = <1>;
flash0: flash@80000000 {
compatible = "soc-nv-flash";
reg = <0x80000000 DT_SIZE_M(1)>;
erase-block-size = <4096>;
write-block-size = <4>;
};
};
sram0: memory@80100000 {
compatible = "mmio-sram";
reg = <0x80100000 DT_SIZE_K(60)>;
};
ilm: ilm@f01040 {
compatible = "ite,it8xxx2-ilm";
reg = <0xf01040 3 /* SCAR0 */
0xf01043 3
0xf01046 3
0xf01049 3
0xf0104c 3 /* SCAR4 */
0xf01081 3 /* SCAR5 */
0xf01084 3
0xf01087 3
0xf0108a 3
0xf0108d 3
0xf01090 3
0xf01093 3
0xf01096 3 /* SCAR12 */
0xf010b0 3 /* SCAR13 */
0xf010b3 3
0xf010b6 3
0xf010b9 3
0xf010bc 3
0xf010bf 3
0xf010c2 3
0xf010c5 3
0xf010c8 3
0xf010cb 3
0xf010ce 3>; /* SCAR23 */
};
uart1: uart@f02700 {
compatible = "ns16550";
reg = <0x00f02700 0x0020>;
status = "disabled";
current-speed = <115200>;
clock-frequency = <1843200>;
interrupts = <38 IRQ_TYPE_EDGE_RISING>;
interrupt-parent = <&intc>;
reg-shift = <0>;
};
uart2: uart@f02800 {
compatible = "ns16550";
reg = <0x00f02800 0x0020>;
status = "disabled";
current-speed = <460800>;
clock-frequency = <1843200>;
interrupts = <39 IRQ_TYPE_EDGE_RISING>;
interrupt-parent = <&intc>;
reg-shift = <0>;
};
ite_uart1_wrapper: uartwrapper@f02720 {
compatible = "ite,it8xxx2-uart";
reg = <0x00f02720 0x0020>;
status = "disabled";
port-num = <1>;
gpios = <&gpiob 0 0>;
uart-dev = <&uart1>;
};
ite_uart2_wrapper: uartwrapper@f02820 {
compatible = "ite,it8xxx2-uart";
reg = <0x00f02820 0x0020>;
status = "disabled";
port-num = <2>;
gpios = <&gpioh 1 0>;
uart-dev = <&uart2>;
};
timer: timer@f01f10 {
compatible = "ite,it8xxx2-timer";
reg = <0x00f01f10 0x0052>;
interrupts = <IT8XXX2_IRQ_TIMER3 IRQ_TYPE_EDGE_RISING /* Event timer */
IT8XXX2_IRQ_TIMER4 IRQ_TYPE_EDGE_RISING /* Free run timer */
IT8XXX2_IRQ_TIMER5 IRQ_TYPE_EDGE_RISING /* Busy wait low */
IT8XXX2_IRQ_TIMER6 IRQ_TYPE_EDGE_RISING /* Busy wait high */
IT8XXX2_IRQ_TIMER7 IRQ_TYPE_EDGE_RISING
IT8XXX2_IRQ_TIMER8 IRQ_TYPE_EDGE_RISING>;
interrupt-parent = <&intc>;
};
gpioa: gpio@f01601 {
compatible = "ite,it8xxx2-gpio";
reg = <0x00f01601 1 /* GPDR (set) */
0x00f01610 8 /* GPCR */
0x00f01661 1 /* GPDMR (get) */
0x00f01671 1>; /* GPOTR */
ngpios = <8>;
gpio-controller;
interrupts = <IT8XXX2_IRQ_WU91 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU92 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU93 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU80 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU81 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU82 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU83 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU100 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intc>;
#gpio-cells = <2>;
};
gpiob: gpio@f01602 {
compatible = "ite,it8xxx2-gpio";
reg = <0x00f01602 1 /* GPDR (set) */
0x00f01618 8 /* GPCR */
0x00f01662 1 /* GPDMR (get) */
0x00f01672 1>; /* GPOTR */
ngpios = <8>;
gpio-controller;
interrupts = <IT8XXX2_IRQ_WU101 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU102 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU84 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU103 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU94 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU104 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU105 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU106 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intc>;
wakeup-source; /* WUI53 */
#gpio-cells = <2>;
};
gpioc: gpio@f01603 {
compatible = "ite,it8xxx2-gpio";
reg = <0x00f01603 1 /* GPDR (set) */
0x00f01620 8 /* GPCR */
0x00f01663 1 /* GPDMR (get) */
0x00f01673 1>; /* GPOTR */
ngpios = <8>;
gpio-controller;
interrupts = <IT8XXX2_IRQ_WU85 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU107 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU95 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU108 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU22 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU109 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU23 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU86 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intc>;
#gpio-cells = <2>;
};
gpiod: gpio@f01604 {
compatible = "ite,it8xxx2-gpio";
reg = <0x00f01604 1 /* GPDR (set) */
0x00f01628 8 /* GPCR */
0x00f01664 1 /* GPDMR (get) */
0x00f01674 1>; /* GPOTR */
ngpios = <8>;
gpio-controller;
interrupts = <IT8XXX2_IRQ_WU20 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU21 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU24 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU110 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU111 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU112 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU113 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU87 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intc>;
#gpio-cells = <2>;
};
gpioe: gpio@f01605 {
compatible = "ite,it8xxx2-gpio";
reg = <0x00f01605 1 /* GPDR (set) */
0x00f01630 8 /* GPCR */
0x00f01665 1 /* GPDMR (get) */
0x00f01675 1>; /* GPOTR */
ngpios = <8>;
gpio-controller;
interrupts = <IT8XXX2_IRQ_WU70 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU71 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU72 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU73 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU114 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU40 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU45 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU46 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intc>;
#gpio-cells = <2>;
};
gpiof: gpio@f01606 {
compatible = "ite,it8xxx2-gpio";
reg = <0x00f01606 1 /* GPDR (set) */
0x00f01638 8 /* GPCR */
0x00f01666 1 /* GPDMR (get) */
0x00f01676 1>; /* GPOTR */
ngpios = <8>;
gpio-controller;
interrupts = <IT8XXX2_IRQ_WU96 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU97 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU98 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU99 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU64 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU65 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU66 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU67 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intc>;
#gpio-cells = <2>;
};
gpiog: gpio@f01607 {
compatible = "ite,it8xxx2-gpio";
reg = <0x00f01607 1 /* GPDR (set) */
0x00f01640 8 /* GPCR */
0x00f01667 1 /* GPDMR (get) */
0x00f01677 1>; /* GPOTR */
ngpios = <8>;
gpio-controller;
interrupts = <IT8XXX2_IRQ_WU115 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU116 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU117 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU123 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU124 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU125 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU118 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU126 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intc>;
#gpio-cells = <2>;
};
gpioh: gpio@f01608 {
compatible = "ite,it8xxx2-gpio";
reg = <0x00f01608 1 /* GPDR (set) */
0x00f01648 8 /* GPCR */
0x00f01668 1 /* GPDMR (get) */
0x00f01678 1>; /* GPOTR */
ngpios = <8>;
gpio-controller;
interrupts = <IT8XXX2_IRQ_WU60 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU61 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU62 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU63 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU88 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU89 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU90 IRQ_TYPE_LEVEL_HIGH
0 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intc>;
wakeup-source; /* WUI17 */
#gpio-cells = <2>;
};
gpioi: gpio@f01609 {
compatible = "ite,it8xxx2-gpio";
reg = <0x00f01609 1 /* GPDR (set) */
0x00f01650 8 /* GPCR */
0x00f01669 1 /* GPDMR (get) */
0x00f01679 1>; /* GPOTR */
ngpios = <8>;
gpio-controller;
interrupts = <IT8XXX2_IRQ_WU119 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU120 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU121 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU122 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU74 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU75 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU76 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU77 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intc>;
#gpio-cells = <2>;
};
gpioj: gpio@f0160a {
compatible = "ite,it8xxx2-gpio";
reg = <0x00f0160a 1 /* GPDR (set) */
0x00f01658 8 /* GPCR */
0x00f0166a 1 /* GPDMR (get) */
0x00f0167a 1>; /* GPOTR */
ngpios = <8>;
gpio-controller;
interrupts = <IT8XXX2_IRQ_WU128 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU129 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU130 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU131 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU132 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU133 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU134 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU135 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intc>;
#gpio-cells = <2>;
};
gpiok: gpio@f0160b {
compatible = "ite,it8xxx2-gpio";
reg = <0x00f0160b 1 /* GPDR (set) */
0x00f01690 8 /* GPCR */
0x00f0166b 1 /* GPDMR (get) */
0x00f0167b 1>; /* GPOTR */
ngpios = <8>;
gpio-controller;
interrupts = <IT8XXX2_IRQ_WU50 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU51 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU52 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU53 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU54 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU55 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU56 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU57 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intc>;
#gpio-cells = <2>;
};
gpiol: gpio@f0160c {
compatible = "ite,it8xxx2-gpio";
reg = <0x00f0160c 1 /* GPDR (set) */
0x00f01698 8 /* GPCR */
0x00f0166c 1 /* GPDMR (get) */
0x00f0167c 1>; /* GPOTR */
ngpios = <8>;
gpio-controller;
interrupts = <IT8XXX2_IRQ_WU136 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU137 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU138 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU139 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU140 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU141 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU142 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU143 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intc>;
#gpio-cells = <2>;
};
gpiom: gpio@f0160d {
compatible = "ite,it8xxx2-gpio";
reg = <0x00f0160d 1 /* GPDR (set) */
0x00f016a0 8 /* GPCR */
0x00f0166d 1 /* GPDMR (get) */
0x00f0167d 1>; /* GPOTR */
ngpios = <7>;
gpio-controller;
interrupts = <IT8XXX2_IRQ_WU144 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU145 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU146 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU147 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU148 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU149 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WU150 IRQ_TYPE_LEVEL_HIGH
0 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intc>;
#gpio-cells = <2>;
};
espi0: espi@f03100 {
compatible = "ite,it8xxx2-espi";
reg = <0x00f03100 0xd8 /* eSPI slave */
0x00f03200 0x9a /* eSPI VW */
0x00f03300 0xd0 /* eSPI Queue 0 */
0x00f03400 0xc0 /* eSPI Queue 1 */
0x00f01200 6 /* EC2I bridge */
0x00f01300 11 /* Host KBC */
0x00f01500 0x100 /* Host PMC */
0x00f01000 0xd1>; /* SMFI */
interrupts = <IT8XXX2_IRQ_ESPI IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_ESPI_VW IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_KBC_IBF IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_KBC_OBE IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_PMC1_IBF IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_PCH_P80 IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_PMC2_IBF IRQ_TYPE_LEVEL_HIGH
IT8XXX2_IRQ_WKINTD IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intc>;
wucctrl = <&wuc_wu42>;
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
};
spi0: spi@f02600 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "ite,it8xxx2-sspi";
reg = <0x00f02600 0x40>;
interrupt-parent = <&intc>;
interrupts = <37 IRQ_TYPE_EDGE_RISING>;
clock-frequency = <115200>;
};
spi1: spi@f02640 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "ite,it8xxx2-sspi";
reg = <0x00f02640 0x40>;
interrupts = <37 IRQ_TYPE_EDGE_RISING>;
interrupt-parent = <&intc>;
status = "okay";
};
shi0: shi@f03a00 {
compatible = "ite,it8xxx2-shi";
reg = <0x00f03a00 0x30>;
interrupts = <171 0>;
interrupt-parent = <&intc>;
status = "disabled";
buffer-rx-size = <256>;
buffer-tx-size = <256>;
};
adc0: adc@f01900 {
compatible = "ite,it8xxx2-adc";
reg = <0xf01900 0x45>;
interrupts = <8 IRQ_TYPE_NONE>;
interrupt-parent = <&intc>;
status = "disabled";
#io-channel-cells = <1>;
};
vcmp0: vcmp@f01946 {
compatible = "ite,it8xxx2-vcmp";
reg = <0xf01946 0x01 /* VCMP0CTL */
0xf01977 0x01 /* VCMP0CSELM */
0xf01937 0x01 /* VCMPSCP */
0xf01947 0x01 /* VCMP0THRDATM */
0xf01948 0x01 /* VCMP0THRDATL */
0xf01945 0x01 /* VCMPSTS */
0xf0196d 0x01>; /* VCMPSTS2 */
interrupts = <IT8XXX2_IRQ_V_CMP IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intc>;
vcmp-ch = <VCMP_CHANNEL_0>;
status = "disabled";
};
vcmp1: vcmp@f01949 {
compatible = "ite,it8xxx2-vcmp";
reg = <0xf01949 0x01 /* VCMP1CTL */
0xf01978 0x01 /* VCMP1CSELM */
0xf01937 0x01 /* VCMPSCP */
0xf0194a 0x01 /* VCMP1THRDATM */
0xf0194b 0x01 /* VCMP1THRDATL */
0xf01945 0x01 /* VCMPSTS */
0xf0196d 0x01>; /* VCMPSTS2 */
interrupts = <IT8XXX2_IRQ_V_CMP IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intc>;
vcmp-ch = <VCMP_CHANNEL_1>;
status = "disabled";
};
vcmp2: vcmp@f0194c {
compatible = "ite,it8xxx2-vcmp";
reg = <0xf0194c 0x01 /* VCMP2CTL */
0xf01979 0x01 /* VCMP2CSELM */
0xf01937 0x01 /* VCMPSCP */
0xf0194d 0x01 /* VCMP2THRDATM */
0xf0194e 0x01 /* VCMP2THRDATL */
0xf01945 0x01 /* VCMPSTS */
0xf0196d 0x01>; /* VCMPSTS2 */
interrupts = <IT8XXX2_IRQ_V_CMP IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intc>;
vcmp-ch = <VCMP_CHANNEL_2>;
status = "disabled";
};
vcmp3: vcmp@f0196e {
compatible = "ite,it8xxx2-vcmp";
reg = <0xf0196e 0x01 /* VCMP3CTL */
0xf0197a 0x01 /* VCMP3CSELM */
0xf01937 0x01 /* VCMPSCP */
0xf0196f 0x01 /* VCMP3THRDATM */
0xf01970 0x01 /* VCMP3THRDATL */
0xf01945 0x01 /* VCMPSTS */
0xf0196d 0x01>; /* VCMPSTS2 */
interrupts = <IT8XXX2_IRQ_V_CMP IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intc>;
vcmp-ch = <VCMP_CHANNEL_3>;
status = "disabled";
};
vcmp4: vcmp@f01971 {
compatible = "ite,it8xxx2-vcmp";
reg = <0xf01971 0x01 /* VCMP4CTL */
0xf0197b 0x01 /* VCMP4CSELM */
0xf01937 0x01 /* VCMPSCP */
0xf01972 0x01 /* VCMP4THRDATM */
0xf01973 0x01 /* VCMP4THRDATL */
0xf01945 0x01 /* VCMPSTS */
0xf0196d 0x01>; /* VCMPSTS2 */
interrupts = <IT8XXX2_IRQ_V_CMP IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intc>;
vcmp-ch = <VCMP_CHANNEL_4>;
status = "disabled";
};
vcmp5: vcmp@f01974 {
compatible = "ite,it8xxx2-vcmp";
reg = <0xf01974 0x01 /* VCMP5CTL */
0xf0197c 0x01 /* VCMP5CSELM */
0xf01937 0x01 /* VCMPSCP */
0xf01975 0x01 /* VCMP5THRDATM */
0xf01976 0x01 /* VCMP5THRDATL */
0xf01945 0x01 /* VCMPSTS */
0xf0196d 0x01>; /* VCMPSTS2 */
interrupts = <IT8XXX2_IRQ_V_CMP IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intc>;
vcmp-ch = <VCMP_CHANNEL_5>;
status = "disabled";
};
ecpm: clock-controller@f01e00 {
compatible = "ite,it8xxx2-ecpm";
reg = <0x00f01e00 0x11>;
reg-names = "ecpm";
};
prs: pwmprs@f01800 {
compatible = "ite,it8xxx2-pwmprs";
reg = <0x00f01800 1>;
};
pwm0: pwm@f01802 {
compatible = "ite,it8xxx2-pwm";
reg = <0x00f01802 1 /* DCR */
0x00f0180c 1 /* PCSSG */
0x00f0180f 1 /* PCSG */
0x00f0180a 1>; /* PWMPOL */
channel = <PWM_CHANNEL_0>;
status = "disabled";
pwmctrl = <&prs>;
#pwm-cells = <3>;
};
pwm1: pwm@f01803 {
compatible = "ite,it8xxx2-pwm";
reg = <0x00f01803 1 /* DCR */
0x00f0180c 1 /* PCSSG */
0x00f0180f 1 /* PCSG */
0x00f0180a 1>; /* PWMPOL */
channel = <PWM_CHANNEL_1>;
status = "disabled";
pwmctrl = <&prs>;
#pwm-cells = <3>;
};
pwm2: pwm@f01804 {
compatible = "ite,it8xxx2-pwm";
reg = <0x00f01804 1 /* DCR */
0x00f0180c 1 /* PCSSG */
0x00f0180f 1 /* PCSG */
0x00f0180a 1>; /* PWMPOL */
channel = <PWM_CHANNEL_2>;
status = "disabled";
pwmctrl = <&prs>;
#pwm-cells = <3>;
};
pwm3: pwm@f01805 {
compatible = "ite,it8xxx2-pwm";
reg = <0x00f01805 1 /* DCR */
0x00f0180c 1 /* PCSSG */
0x00f0180f 1 /* PCSG */
0x00f0180a 1>; /* PWMPOL */
channel = <PWM_CHANNEL_3>;
status = "disabled";
pwmctrl = <&prs>;
#pwm-cells = <3>;
};
pwm4: pwm@f01806 {
compatible = "ite,it8xxx2-pwm";
reg = <0x00f01806 1 /* DCR */
0x00f0180d 1 /* PCSSG */
0x00f0180f 1 /* PCSG */
0x00f0180a 1>; /* PWMPOL */
channel = <PWM_CHANNEL_4>;
status = "disabled";
pwmctrl = <&prs>;
#pwm-cells = <3>;
};
pwm5: pwm@f01807 {
compatible = "ite,it8xxx2-pwm";
reg = <0x00f01807 1 /* DCR */
0x00f0180d 1 /* PCSSG */
0x00f0180f 1 /* PCSG */
0x00f0180a 1>; /* PWMPOL */
channel = <PWM_CHANNEL_5>;
status = "disabled";
pwmctrl = <&prs>;
#pwm-cells = <3>;
};
pwm6: pwm@f01808 {
compatible = "ite,it8xxx2-pwm";
reg = <0x00f01808 1 /* DCR */
0x00f0180d 1 /* PCSSG */
0x00f0180f 1 /* PCSG */
0x00f0180a 1>; /* PWMPOL */
channel = <PWM_CHANNEL_6>;
status = "disabled";
pwmctrl = <&prs>;
#pwm-cells = <3>;
};
pwm7: pwm@f01809 {
compatible = "ite,it8xxx2-pwm";
reg = <0x00f01809 1 /* DCR */
0x00f0180d 1 /* PCSSG */
0x00f0180f 1 /* PCSG */
0x00f0180a 1>; /* PWMPOL */
channel = <PWM_CHANNEL_7>;
status = "disabled";
pwmctrl = <&prs>;
#pwm-cells = <3>;
};
tach0: tach@f0181e {
compatible = "ite,it8xxx2-tach";
reg = <0x00f0181e 1 /* F1TLRR */
0x00f0181f 1 /* F1TMRR */
0x00f01848 1>; /* TSWCTLR */
dvs-bit = <BIT(3)>;
chsel-bit = <BIT(2)>;
status = "disabled";
};
tach1: tach@f01820 {
compatible = "ite,it8xxx2-tach";
reg = <0x00f01820 1 /* F2TLRR */
0x00f01821 1 /* F2TMRR */
0x00f01848 1>; /* TSWCTLR */
dvs-bit = <BIT(1)>;
chsel-bit = <BIT(0)>;
status = "disabled";
};
gctrl: general-control@f02000 {
compatible = "ite,it8xxx2-gctrl";
reg = <0x00f02000 0x100>;
};
peci0: peci@f02c00 {
compatible = "ite,it8xxx2-peci";
reg = <0x00f02c00 15>;
#address-cells=<1>;
#size-cells = <0>;
interrupt-parent = <&intc>;
interrupts = <160 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
kbd: kbd@f01d00 {
compatible = "ite,it8xxx2-kbd";
reg = <0x00f01d00 0x29>;
interrupt-parent = <&intc>;
interrupts = <IT8XXX2_IRQ_WKINTC IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
wucctrl = <&wuc_wu30 /* KSI[0] */
&wuc_wu31 /* KSI[1] */
&wuc_wu32 /* KSI[2] */
&wuc_wu33 /* KSI[3] */
&wuc_wu34 /* KSI[4] */
&wuc_wu35 /* KSI[5] */
&wuc_wu36 /* KSI[6] */
&wuc_wu37>; /* KSI[7] */
kso16-gpios = <&gpioc 3 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>;
kso17-gpios = <&gpioc 5 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>;
};
sha0: sha@f0202d {
compatible = "ite,it8xxx2-sha";
reg = <0x00f0202d 0x3>;
status = "disabled";
};
usbpd0: usbpd@f03700 {
compatible = "ite,it8xxx2-usbpd";
reg = <0x00f03700 0x100>;
status = "disabled";
};
usbpd1: usbpd@f03800 {
compatible = "ite,it8xxx2-usbpd";
reg = <0x00f03800 0x100>;
status = "disabled";
};
};
};
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