zephyr/dts/riscv
Tim Lin a0a599b54b ITE: drivers/pinctrl: Distinguish between func3-gcr and func3-ext settings
This PR separates the GCTRL settings from func3-gcr to func3-ext.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2024-01-26 14:21:34 -05:00
..
andes
efinix
espressif/esp32c3
gd soc: riscv: gd32vf103: simplify MCAUSE exception mask handling 2024-01-15 09:58:03 +01:00
ite ITE: drivers/pinctrl: Distinguish between func3-gcr and func3-ext settings 2024-01-26 14:21:34 -05:00
lowrisc
microchip
niosv
openisa
sifive dts: riscv: sifive: fu540: add missing ngpios property 2024-01-19 15:13:53 +00:00
starfive
telink
neorv32.dtsi
renode_riscv32_virt.dtsi dts: riscv: add a SoC dtsi for Renode RISC-V Virt SoC 2024-01-08 12:35:10 +01:00
riscv32-litex-vexriscv.dtsi
virt.dtsi