0a3fe40505
Define the edge-trigger register base address based on whether the PLIC node in the devicetree has an additional compatible that supports edge-triggered interrupt. Limited the implementation to Andes NCEPLIC100 only, updated the devicetree binding of `andes_v5_ae350` accordingly. Signed-off-by: Yong Cong Sin <ycsin@meta.com> |
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andes_v5_ae350.dtsi |