68 lines
3.0 KiB
C
68 lines
3.0 KiB
C
/* SoC level DTS fixup file */
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#define DT_UART_NS16550_PORT_0_BASE_ADDR DT_NS16550_80800_BASE_ADDRESS
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#define CONFIG_UART_NS16550_PORT_0_BAUD_RATE DT_NS16550_80800_CURRENT_SPEED
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#define CONFIG_UART_NS16550_PORT_0_NAME DT_NS16550_80800_LABEL
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#define DT_UART_NS16550_PORT_0_IRQ DT_NS16550_80800_IRQ_0
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#define CONFIG_UART_NS16550_PORT_0_IRQ_PRI DT_NS16550_80800_IRQ_0_PRIORITY
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#define DT_UART_NS16550_PORT_0_IRQ_FLAGS DT_NS16550_80800_IRQ_0_SENSE
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#define DT_UART_NS16550_PORT_0_CLK_FREQ DT_NS16550_80800_CLOCK_FREQUENCY
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#define DT_L2_SRAM_BASE DT_SRAM_BASE_ADDRESS
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#define DT_L2_SRAM_SIZE DT_SRAM_SIZE * 1024
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#define DT_CAVS_ICTL_BASE_ADDR DT_INTEL_CAVS_INTC_78800_BASE_ADDRESS
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#define DT_CAVS_ICTL_0_IRQ DT_INTEL_CAVS_INTC_78800_IRQ_0
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#define DT_CAVS_ICTL_0_IRQ_PRI DT_INTEL_CAVS_INTC_78800_IRQ_0_PRIORITY
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#define DT_CAVS_ICTL_0_IRQ_FLAGS DT_INTEL_CAVS_INTC_78800_IRQ_0_SENSE
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#define DT_CAVS_ICTL_1_IRQ DT_INTEL_CAVS_INTC_78810_IRQ_0
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#define DT_CAVS_ICTL_1_IRQ_PRI DT_INTEL_CAVS_INTC_78810_IRQ_0_PRIORITY
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#define DT_CAVS_ICTL_1_IRQ_FLAGS DT_INTEL_CAVS_INTC_78810_IRQ_0_SENSE
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#define DT_CAVS_ICTL_2_IRQ DT_INTEL_CAVS_INTC_78820_IRQ_0
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#define DT_CAVS_ICTL_2_IRQ_PRI DT_INTEL_CAVS_INTC_78820_IRQ_0_PRIORITY
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#define DT_CAVS_ICTL_2_IRQ_FLAGS DT_INTEL_CAVS_INTC_78820_IRQ_0_SENSE
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#define DT_CAVS_ICTL_3_IRQ DT_INTEL_CAVS_INTC_78830_IRQ_0
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#define DT_CAVS_ICTL_3_IRQ_PRI DT_INTEL_CAVS_INTC_78830_IRQ_0_PRIORITY
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#define DT_CAVS_ICTL_3_IRQ_FLAGS DT_INTEL_CAVS_INTC_78830_IRQ_0_SENSE
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#define DT_DW_ICTL_BASE_ADDR DT_SNPS_DESIGNWARE_INTC_81800_BASE_ADDRESS
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#define DT_DW_ICTL_IRQ ((DT_SNPS_DESIGNWARE_INTC_81800_IRQ_0 << 8) | \
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(DT_INTEL_CAVS_INTC_78800_IRQ_0 << 0))
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#define DT_DW_ICTL_IRQ_PRI DT_SNPS_DESIGNWARE_INTC_81800_IRQ_0_PRIORITY
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#define DT_DW_ICTL_IRQ_FLAGS DT_SNPS_DESIGNWARE_INTC_81800_IRQ_0_SENSE
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#define DT_SPI_0_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_E000_BASE_ADDRESS
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#define DT_SPI_0_NAME DT_SNPS_DESIGNWARE_SPI_E000_LABEL
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#define DT_SPI_0_IRQ DT_SNPS_DESIGNWARE_SPI_E000_IRQ_0
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#define DT_SPI_DW_IRQ_FLAGS DT_SNPS_DESIGNWARE_SPI_E000_IRQ_0_SENSE
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#define DT_SPI_0_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_E000_IRQ_0_PRIORITY
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#define DT_GPIO_DW_0_BASE_ADDR \
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DT_SNPS_DESIGNWARE_GPIO_80C00_BASE_ADDRESS
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#define DT_GPIO_DW_0_BITS \
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DT_SNPS_DESIGNWARE_GPIO_80C00_BITS
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#define DT_GPIO_INTC_IRQ \
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(DT_SNPS_DESIGNWARE_GPIO_80C00_IRQ_0 << INTR_CNTL_IRQ_NUM_SHIFT)
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#define DT_GPIO_CAVS_IRQ \
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(DT_SNPS_DESIGNWARE_INTC_81800_IRQ_0 << CAVS_IRQ_NUM_SHIFT)
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#define DT_GPIO_XTENSA_IRQ \
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(DT_INTEL_CAVS_INTC_78800_IRQ_0 << XTENSA_IRQ_NUM_SHIFT)
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#define DT_GPIO_DW_0_IRQ \
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(DT_GPIO_INTC_IRQ | DT_GPIO_CAVS_IRQ | DT_GPIO_XTENSA_IRQ)
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#define CONFIG_GPIO_DW_0_IRQ_PRI \
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DT_SNPS_DESIGNWARE_GPIO_80C00_IRQ_0_PRIORITY
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#define DT_GPIO_DW_0_IRQ_FLAGS 0
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#define CONFIG_GPIO_DW_0_NAME \
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DT_SNPS_DESIGNWARE_GPIO_80C00_LABEL
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#define DT_PINMUX_BASE_ADDR \
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DT_INTEL_S1000_PINMUX_81C30_BASE_ADDRESS
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#define DT_PINMUX_CTRL_REG_COUNT \
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(DT_INTEL_S1000_PINMUX_81C30_SIZE / 4)
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/* End of SoC Level DTS fixup file */
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