Kamil Galik 385ad46a39 boards/xtensa: Skip cleaning intermediate binaries up ... This commit removes `CONFIG_CLEANUP_INTERMEDIATE_FILES` y-selection from some Xtensa board configs. Y-selecting this option causes `west spdx` to fail, due to reasons described in `CONFIG_CLEANUP_INTERMEDIATE_FILES` help string. If CLEANUP_INTERMEDIATE_FILES is y-selected, build files are removed from the `cfgTarget.target.artifacts` list. This in turn causes the `addBuildFile` function to nod add them to `pkg`, so `pkg.targetBuildFile` is `None` in `scripts/west_commands/zspdx/walker.py`. This causes the `west spdx` command to fail. Signed-off-by: Kamil Galik <kgalik@internships.antmicro.com> Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>		2023-07-19 20:46:51 -04:00
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doc	boards: xtensa: update rimage and west sign documentation	2023-06-02 15:07:59 -04:00
Kconfig.board	…
Kconfig.defconfig	…
board.cmake	west: sign: add new west config [rimage].extra-args and a default key	2023-04-10 22:04:47 -04:00
intel_adsp_cavs25.dts	…
intel_adsp_cavs25.yaml	yamllint: indentation: fix files in boards/	2023-01-04 14:23:53 +01:00
intel_adsp_cavs25_defconfig	boards/xtensa: Skip cleaning intermediate binaries up	2023-07-19 20:46:51 -04:00
intel_adsp_cavs25_tgph.dts	…
intel_adsp_cavs25_tgph.yaml	yamllint: indentation: fix files in boards/	2023-01-04 14:23:53 +01:00
intel_adsp_cavs25_tgph_defconfig	boards/xtensa: Skip cleaning intermediate binaries up	2023-07-19 20:46:51 -04:00
pre_dt_board.cmake	…