Kai Vehmanen e0bcf9f959 xtensa: cavs: add uncached ram sections to cavs25 linker script ... Align cavs25 with cavs15/18 and add memory segment for uncached mapping of the SRAM to linker script. Assign sections to uncached and cached segments as done in cavs15/18. Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>		2021-06-14 21:48:44 -04:00
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cavs_v15	soc: xtensa: linker: Update linker scripts for C++ build	2021-05-28 09:32:44 -05:00
cavs_v18	soc: xtensa: linker: Update linker scripts for C++ build	2021-05-28 09:32:44 -05:00
cavs_v20	soc: xtensa: linker: Update linker scripts for C++ build	2021-05-28 09:32:44 -05:00
cavs_v25	xtensa: cavs: add uncached ram sections to cavs25 linker script	2021-06-14 21:48:44 -04:00
common	xtensa: fix delayed booting secondary cores	2021-05-03 17:13:01 -04:00
CMakeLists.txt	xtensa: set toolchain variant per SoC	2020-12-20 14:30:50 -05:00
Kconfig	soc/intel_adsp: Move KERNEL_COHERENCE to cavs15	2021-02-11 14:47:40 -05:00
Kconfig.defconfig	…
Kconfig.soc	…