18 lines
487 B
C
18 lines
487 B
C
/*
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* Copyright (c) 2018 - 2019 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __RISCV32_LITEX_VEXRISCV_SOC_H_
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#define __RISCV32_LITEX_VEXRISCV_SOC_H_
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#include "../riscv-privilege/common/soc_common.h"
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#include <generated_dts_board.h>
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/* lib-c hooks required RAM defined variables */
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#define RISCV_RAM_BASE DT_MMIO_SRAM_0_BASE_ADDRESS
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#define RISCV_RAM_SIZE DT_MMIO_SRAM_0_SIZE
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#endif /* __RISCV32_LITEX_VEXRISCV_SOC_H_ */
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