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zephyr/soc/riscv32
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Lyle Zhu 34b0516466 boards: riscv32: rv32m1_vega: enable MCUboot for ri5cy core 
1. Add flash partitions.
2. Add macro DT_START_UP_ENTRY_OFFSET. The entry of the RV32M1 is
   not the start of the vector table. Add the macro to inform the
   entry offset.
3. Update linker file to support MCUboot
   a. For normal cases (CONFIG_BOOTLOADER_MCUBOOT is cleared), the
   vector table is located last 256bytes of the flash.
   b. If CONFIG_BOOTLOADER_MCUBOOT is set, the vector table is located
   after the image header of MCUboot.

Signed-off-by: Lyle Zhu <lyle.zhu@nxp.com>
 		2019-06-03 10:43:47 -05:00
..
litex-vexriscv soc: riscv32: add LiteX VexRiscV SoC 2019-05-15 12:52:16 -05:00
openisa_rv32m1 boards: riscv32: rv32m1_vega: enable MCUboot for ri5cy core 2019-06-03 10:43:47 -05:00
riscv-privilege drivers/plic: Remove DTS fixups for RISC-V PLIC 2019-05-30 18:40:26 -04:00
CMakeLists.txt license: cleanup: add SPDX Apache-2.0 license identifier 2019-04-07 08:45:22 -04:00