161 lines
2.9 KiB
Plaintext
161 lines
2.9 KiB
Plaintext
/*
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* Copyright (c) 2019, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <arm/armv8-m.dtsi>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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aliases {
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gpio-0 = &gpio0;
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gpio-1 = &gpio1;
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gpio-2 = &gpio2;
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gpio-3 = &gpio3;
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spi-8 = &spi8;
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usart-0 = &usart0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-m33f";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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mpu: mpu@e000ed90 {
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compatible = "arm,armv8m-mpu";
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reg = <0xe000ed90 0x40>;
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arm,num-mpu-regions = <8>;
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};
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};
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cpu@1 {
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compatible = "arm,cortex-m33";
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reg = <1>;
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};
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};
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sram0: memory@30000000 {
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compatible = "mmio-sram";
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reg = <0x30000000 DT_SIZE_K(64)>;
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};
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sram1: memory@30010000 {
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compatible = "mmio-sram";
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reg = <0x30010000 DT_SIZE_K(64)>;
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};
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sram2: memory@30020000 {
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compatible = "mmio-sram";
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reg = <0x30020000 DT_SIZE_K(64)>;
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};
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sram3: memory@30030000 {
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compatible = "mmio-sram";
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reg = <0x30030000 DT_SIZE_K(64)>;
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};
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sram4: memory@30040000 {
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/* Conencted to USB bus*/
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compatible = "mmio-sram";
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reg = <0x30040000 DT_SIZE_K(16)>;
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};
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sramx: memory@14000000 {
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/* connected to code bus */
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compatible = "mmio-sram";
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reg = <0x14000000 DT_SIZE_K(32)>;
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};
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soc {
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flash-controller@50034000 {
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compatible = "nxp,lpc-iap";
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label = "FLASH_IAP";
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reg = <0x50034000 0x18>;
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#address-cells = <1>;
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#size-cells = <1>;
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flash0: flash@10000000 {
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compatible = "soc-nv-flash";
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label = "MCUX_FLASH";
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reg = <0x10000000 DT_SIZE_K(630)>;
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erase-block-size = <512>;
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write-block-size = <512>;
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};
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flash_reserved: flash@1009D800 {
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compatible = "soc-nv-flash";
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reg = <0x1009D800 DT_SIZE_K(10)>;
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status = "disabled";
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};
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boot_rom: flash@13000000 {
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compatible = "soc-nv-flash";
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reg = <0x13000000 DT_SIZE_K(128)>;
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};
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};
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usart0: usart@50086000 {
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compatible = "nxp,lpc-usart";
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reg = <0x50086000 0xE44>;
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interrupts = <14 0>;
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label = "USART_0";
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status = "disabled";
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};
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gpio0: gpio@0 {
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compatible = "nxp,lpc-gpio";
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reg = <0x5008c000 0x2488>;
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interrupts = <4 2>,<5 2>,<6 2>,<7 2>;
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label = "GPIO_0";
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio1: gpio@1 {
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compatible = "nxp,lpc-gpio";
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reg = <0x5008c000 0x2488>;
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interrupts = <32 2>,<33 2>,<34 2>,<35 2>;
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label = "GPIO_1";
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio2: gpio@2 {
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compatible = "nxp,lpc-gpio";
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reg = <0x5008c000 0x2488>;
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label = "GPIO_2";
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio3: gpio@3 {
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compatible = "nxp,lpc-gpio";
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reg = <0x5008c000 0x2488>;
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label = "GPIO_3";
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gpio-controller;
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#gpio-cells = <2>;
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};
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spi8: spi@5009f000 {
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compatible = "nxp,lpc-spi";
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reg = <0x5009f000 0x1000>;
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interrupts = <59 0>;
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label = "SPI_8";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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