317 lines
8.4 KiB
C
317 lines
8.4 KiB
C
/*
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* Copyright (c) 2020 IoT.bzh
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT renesas_rcar_gpio
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#include <errno.h>
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#include <zephyr/init.h>
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/clock_control/renesas_cpg_mssr.h>
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#include <zephyr/irq.h>
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#include <zephyr/drivers/gpio/gpio_utils.h>
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typedef void (*init_func_t)(const struct device *dev);
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/* Required by DEVICE_MMIO_NAMED_* macros */
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#define DEV_CFG(_dev) \
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((const struct gpio_rcar_cfg *)(_dev)->config)
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#define DEV_DATA(_dev) ((struct gpio_rcar_data *)(_dev)->data)
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struct gpio_rcar_cfg {
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struct gpio_driver_config common;
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DEVICE_MMIO_NAMED_ROM(reg_base);
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init_func_t init_func;
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const struct device *clock_dev;
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struct rcar_cpg_clk mod_clk;
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};
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struct gpio_rcar_data {
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struct gpio_driver_data common;
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DEVICE_MMIO_NAMED_RAM(reg_base);
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sys_slist_t cb;
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};
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#define IOINTSEL 0x00 /* General IO/Interrupt Switching Register */
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#define INOUTSEL 0x04 /* General Input/Output Switching Register */
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#define OUTDT 0x08 /* General Output Register */
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#define INDT 0x0c /* General Input Register */
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#define INTDT 0x10 /* Interrupt Display Register */
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#define INTCLR 0x14 /* Interrupt Clear Register */
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#define INTMSK 0x18 /* Interrupt Mask Register */
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#define MSKCLR 0x1c /* Interrupt Mask Clear Register */
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#define POSNEG 0x20 /* Positive/Negative Logic Select Register */
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#define EDGLEVEL 0x24 /* Edge/level Select Register */
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#define FILONOFF 0x28 /* Chattering Prevention On/Off Register */
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#define OUTDTSEL 0x40 /* Output Data Select Register */
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#define BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */
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static inline uint32_t gpio_rcar_read(const struct device *dev, uint32_t offs)
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{
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return sys_read32(DEVICE_MMIO_NAMED_GET(dev, reg_base) + offs);
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}
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static inline void gpio_rcar_write(const struct device *dev, uint32_t offs, uint32_t value)
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{
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sys_write32(value, DEVICE_MMIO_NAMED_GET(dev, reg_base) + offs);
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}
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static void gpio_rcar_modify_bit(const struct device *dev,
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uint32_t offs, int bit, bool value)
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{
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uint32_t tmp = gpio_rcar_read(dev, offs);
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if (value) {
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tmp |= BIT(bit);
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} else {
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tmp &= ~BIT(bit);
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}
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gpio_rcar_write(dev, offs, tmp);
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}
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static void gpio_rcar_port_isr(const struct device *dev)
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{
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struct gpio_rcar_data *data = dev->data;
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uint32_t pending, fsb, mask;
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pending = gpio_rcar_read(dev, INTDT);
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mask = gpio_rcar_read(dev, INTMSK);
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while ((pending = gpio_rcar_read(dev, INTDT) &
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gpio_rcar_read(dev, INTMSK))) {
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fsb = find_lsb_set(pending) - 1;
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gpio_fire_callbacks(&data->cb, dev, BIT(fsb));
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gpio_rcar_write(dev, INTCLR, BIT(fsb));
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}
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}
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static void gpio_rcar_config_general_input_output_mode(
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const struct device *dev,
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uint32_t gpio,
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bool output)
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{
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/* follow steps in the GPIO documentation for
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* "Setting General Output Mode" and
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* "Setting General Input Mode"
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*/
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/* Configure positive logic in POSNEG */
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gpio_rcar_modify_bit(dev, POSNEG, gpio, false);
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/* Select "General Input/Output Mode" in IOINTSEL */
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gpio_rcar_modify_bit(dev, IOINTSEL, gpio, false);
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/* Select Input Mode or Output Mode in INOUTSEL */
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gpio_rcar_modify_bit(dev, INOUTSEL, gpio, output);
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/* Select General Output Register to output data in OUTDTSEL */
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if (output) {
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gpio_rcar_modify_bit(dev, OUTDTSEL, gpio, false);
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}
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}
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static int gpio_rcar_configure(const struct device *dev,
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gpio_pin_t pin, gpio_flags_t flags)
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{
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if ((flags & GPIO_OUTPUT) && (flags & GPIO_INPUT)) {
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/* Pin cannot be configured as input and output */
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return -ENOTSUP;
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} else if (!(flags & (GPIO_INPUT | GPIO_OUTPUT))) {
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/* Pin has to be configured as input or output */
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return -ENOTSUP;
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}
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if (flags & GPIO_OUTPUT) {
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if (flags & GPIO_OUTPUT_INIT_HIGH) {
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gpio_rcar_modify_bit(dev, OUTDT, pin, true);
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} else if (flags & GPIO_OUTPUT_INIT_LOW) {
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gpio_rcar_modify_bit(dev, OUTDT, pin, false);
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}
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gpio_rcar_config_general_input_output_mode(dev, pin, true);
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} else {
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gpio_rcar_config_general_input_output_mode(dev, pin, false);
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}
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return 0;
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}
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static int gpio_rcar_port_get_raw(const struct device *dev,
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gpio_port_value_t *value)
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{
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*value = gpio_rcar_read(dev, INDT);
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return 0;
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}
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static int gpio_rcar_port_set_masked_raw(const struct device *dev,
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gpio_port_pins_t mask,
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gpio_port_value_t value)
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{
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uint32_t port_val;
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port_val = gpio_rcar_read(dev, OUTDT);
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port_val = (port_val & ~mask) | (value & mask);
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gpio_rcar_write(dev, OUTDT, port_val);
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return 0;
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}
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static int gpio_rcar_port_set_bits_raw(const struct device *dev,
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gpio_port_pins_t pins)
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{
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uint32_t port_val;
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port_val = gpio_rcar_read(dev, OUTDT);
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port_val |= pins;
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gpio_rcar_write(dev, OUTDT, port_val);
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return 0;
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}
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static int gpio_rcar_port_clear_bits_raw(const struct device *dev,
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gpio_port_pins_t pins)
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{
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uint32_t port_val;
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port_val = gpio_rcar_read(dev, OUTDT);
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port_val &= ~pins;
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gpio_rcar_write(dev, OUTDT, port_val);
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return 0;
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}
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static int gpio_rcar_port_toggle_bits(const struct device *dev,
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gpio_port_pins_t pins)
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{
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uint32_t port_val;
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port_val = gpio_rcar_read(dev, OUTDT);
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port_val ^= pins;
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gpio_rcar_write(dev, OUTDT, port_val);
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return 0;
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}
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static int gpio_rcar_pin_interrupt_configure(const struct device *dev,
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gpio_pin_t pin,
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enum gpio_int_mode mode,
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enum gpio_int_trig trig)
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{
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if (mode == GPIO_INT_MODE_DISABLED) {
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return -ENOTSUP;
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}
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/* Configure positive or negative logic in POSNEG */
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gpio_rcar_modify_bit(dev, POSNEG, pin,
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(trig == GPIO_INT_TRIG_LOW));
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/* Configure edge or level trigger in EDGLEVEL */
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if (mode == GPIO_INT_MODE_EDGE) {
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gpio_rcar_modify_bit(dev, EDGLEVEL, pin, true);
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} else {
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gpio_rcar_modify_bit(dev, EDGLEVEL, pin, false);
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}
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if (trig == GPIO_INT_TRIG_BOTH) {
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gpio_rcar_modify_bit(dev, BOTHEDGE, pin, true);
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}
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gpio_rcar_modify_bit(dev, IOINTSEL, pin, true);
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if (mode == GPIO_INT_MODE_EDGE) {
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/* Write INTCLR in case of edge trigger */
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gpio_rcar_write(dev, INTCLR, BIT(pin));
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}
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gpio_rcar_write(dev, MSKCLR, BIT(pin));
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return 0;
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}
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static int gpio_rcar_init(const struct device *dev)
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{
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const struct gpio_rcar_cfg *config = dev->config;
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int ret;
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if (!device_is_ready(config->clock_dev)) {
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return -ENODEV;
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}
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ret = clock_control_on(config->clock_dev,
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(clock_control_subsys_t) &config->mod_clk);
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if (ret < 0) {
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return ret;
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}
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DEVICE_MMIO_NAMED_MAP(dev, reg_base, K_MEM_CACHE_NONE);
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config->init_func(dev);
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return 0;
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}
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static int gpio_rcar_manage_callback(const struct device *dev,
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struct gpio_callback *callback,
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bool set)
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{
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struct gpio_rcar_data *data = dev->data;
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return gpio_manage_callback(&data->cb, callback, set);
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}
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static const struct gpio_driver_api gpio_rcar_driver_api = {
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.pin_configure = gpio_rcar_configure,
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.port_get_raw = gpio_rcar_port_get_raw,
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.port_set_masked_raw = gpio_rcar_port_set_masked_raw,
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.port_set_bits_raw = gpio_rcar_port_set_bits_raw,
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.port_clear_bits_raw = gpio_rcar_port_clear_bits_raw,
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.port_toggle_bits = gpio_rcar_port_toggle_bits,
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.pin_interrupt_configure = gpio_rcar_pin_interrupt_configure,
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.manage_callback = gpio_rcar_manage_callback,
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};
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/* Device Instantiation */
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#define GPIO_RCAR_INIT(n) \
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static void gpio_rcar_##n##_init(const struct device *dev); \
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static const struct gpio_rcar_cfg gpio_rcar_cfg_##n = { \
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DEVICE_MMIO_NAMED_ROM_INIT(reg_base, DT_DRV_INST(n)), \
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.common = { \
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.port_pin_mask = \
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GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \
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}, \
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.init_func = gpio_rcar_##n##_init, \
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.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
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.mod_clk.module = \
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DT_INST_CLOCKS_CELL_BY_IDX(n, 0, module), \
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.mod_clk.domain = \
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DT_INST_CLOCKS_CELL_BY_IDX(n, 0, domain), \
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}; \
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static struct gpio_rcar_data gpio_rcar_data_##n; \
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\
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DEVICE_DT_INST_DEFINE(n, \
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gpio_rcar_init, \
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NULL, \
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&gpio_rcar_data_##n, \
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&gpio_rcar_cfg_##n, \
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PRE_KERNEL_1, \
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CONFIG_GPIO_INIT_PRIORITY, \
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&gpio_rcar_driver_api \
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); \
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static void gpio_rcar_##n##_init(const struct device *dev) \
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{ \
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IRQ_CONNECT(DT_INST_IRQN(n), \
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0, \
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gpio_rcar_port_isr, \
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DEVICE_DT_INST_GET(n), 0); \
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\
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irq_enable(DT_INST_IRQN(n)); \
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}
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DT_INST_FOREACH_STATUS_OKAY(GPIO_RCAR_INIT)
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