zephyr/soc/xtensa
Lucas Tamborrino 11fc182315 soc: esp32: refactor esp32_net
SOC_ESP32_NET is now SOC_ESP32_APPCPU, following espressif's
naming convention in the same manner as ESP32S3 app cpu.

SOC_ESP32_APPCU is now a subset of SOC_SERIES_ESP32.

This commit also changes the necessary files, samples and tests
for bisect purposes.

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
2024-01-13 00:22:24 +00:00
..
dc233c xtensa: dc233c: force invalidating TLBs during page table swap 2023-12-27 15:59:05 +00:00
espressif_esp32 soc: esp32: refactor esp32_net 2024-01-13 00:22:24 +00:00
intel_adsp intel_adsp: ace15: Enhance HST domain power-down sequence 2024-01-11 10:05:12 +01:00
nxp_adsp xtensa: rename z_xtensa_irq to simple xtensa_irq 2023-12-13 09:41:24 +01:00
sample_controller cmake: cleanup and simplify the standard include logic in Zephyr 2023-11-06 18:57:30 -05:00
CMakeLists.txt