zephyr/soc/xtensa/intel_adsp
Tomasz Leman 1c0c900cbb intel_adsp: ace15: Enhance HST domain power-down sequence
This patch enhances the power-down sequence for the HOST (HST) domain
within the Intel ADSP ACE 1.5 architecture. It introduces a check to
ensure that a specific condition, represented by a magic key value, is
met before disabling the HST domain. This additional verification step
ensures that the HST domain is only powered down when it is safe to do
so, thereby maintaining the stability and reliability of the system.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2024-01-11 10:05:12 +01:00
..
ace intel_adsp: ace15: Enhance HST domain power-down sequence 2024-01-11 10:05:12 +01:00
cavs xtensa: rename z_xtensa_irq to simple xtensa_irq 2023-12-13 09:41:24 +01:00
common intel_adsp: ipc: pm action in busy state 2024-01-06 14:17:15 +01:00
tools intel_adsp: ace: add firmware loading tool 2023-12-11 09:58:18 +01:00
CMakeLists.txt cmake: cleanup and simplify the standard include logic in Zephyr 2023-11-06 18:57:30 -05:00
Kconfig intel_adsp: power: clock gating in idle 2023-12-12 10:57:07 +01:00
Kconfig.defconfig
Kconfig.soc