89 lines
1.5 KiB
Plaintext
89 lines
1.5 KiB
Plaintext
/*
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* Copyright 2022-2023 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <nxp/s32/S32Z27-BGA594-pinctrl.h>
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&pinctrl {
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uart0_default: uart0_default {
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group1 {
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pinmux = <PB10_LIN_0_TX>;
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output-enable;
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};
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group2 {
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pinmux = <PB11_LIN_0_RX>;
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input-enable;
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};
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};
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uart9_default: uart9_default {
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group1 {
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pinmux = <PM6_LIN_9_TX>;
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output-enable;
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};
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group2 {
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pinmux = <PM7_LIN_9_RX>;
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input-enable;
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};
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};
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emdio_default: emdio_default {
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group1 {
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pinmux = <(PE10_ETH_MDC_I | PE10_ETH_MDC_O)>;
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input-enable;
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output-enable;
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};
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group2 {
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pinmux = <(PE11_ETH_MDIO_I | PE11_ETH_MDIO_O)>;
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input-enable;
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output-enable;
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drive-open-drain;
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};
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};
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eth0_default: eth0_default {
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group1 {
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pinmux = <PF2_ETH_0_RX_CLK>,
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<PF3_ETH_0_RGMII_RXCTL>,
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<PF4_ETH_0_RGMII_RXD_0>,
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<PF5_ETH_0_RGMII_RXD_1>,
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<PF6_ETH_0_RGMII_RXD_2>,
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<PF7_ETH_0_RGMII_RXD_3>;
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input-enable;
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};
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group2 {
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pinmux = <PE12_ETH_0_RGMII_TXC>,
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<PE13_ETH_0_RGMII_TXCTL>,
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<PE14_ETH_0_RGMII_TXD_0>,
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<PE15_ETH_0_RGMII_TXD_1>,
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<PF0_ETH_0_RGMII_TXD_2>,
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<PF1_ETH_0_RGMII_TXD_3>;
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output-enable;
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};
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};
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can0_default: can0_default {
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group1 {
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pinmux = <PN2_CANXL_0_RX>;
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input-enable;
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};
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group2 {
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pinmux = <PN1_CANXL_0_TX>;
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output-enable;
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};
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};
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can1_default: can1_default {
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group1 {
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pinmux = <PM11_CANXL_1_RX>;
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input-enable;
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};
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group2 {
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pinmux = <PM10_CANXL_1_TX>;
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output-enable;
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};
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};
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};
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