156 lines
3.8 KiB
C
156 lines
3.8 KiB
C
/*
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* Copyright (c) 2022 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <errno.h>
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#include <zephyr/device.h>
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#include <zephyr/kernel.h>
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#include <zephyr/spinlock.h>
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#include <zephyr/sys/util.h>
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#include <adsp_clk.h>
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#include <adsp_shim.h>
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static struct adsp_cpu_clock_info platform_cpu_clocks[CONFIG_MP_MAX_NUM_CPUS];
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static struct k_spinlock lock;
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int adsp_clock_freq_enc[] = ADSP_CPU_CLOCK_FREQ_ENC;
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int adsp_clock_freq_mask[] = ADSP_CPU_CLOCK_FREQ_MASK;
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#define HW_CLK_CHANGE_TIMEOUT_USEC 10000
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static void select_cpu_clock_hw(uint32_t freq_idx)
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{
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uint32_t enc = adsp_clock_freq_enc[freq_idx];
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#ifdef CONFIG_SOC_SERIES_INTEL_ACE
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uint32_t clk_ctl = ADSP_CLKCTL;
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clk_ctl &= ~ADSP_CLKCTL_OSC_SOURCE_MASK;
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clk_ctl |= (enc & ADSP_CLKCTL_OSC_SOURCE_MASK);
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ADSP_CLKCTL = clk_ctl;
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#else
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uint32_t status_mask = adsp_clock_freq_mask[freq_idx];
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/* Request clock */
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ADSP_CLKCTL |= enc;
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/* Wait for requested clock to be on */
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if (!WAIT_FOR((ADSP_CLKCTL & status_mask) == status_mask,
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HW_CLK_CHANGE_TIMEOUT_USEC, k_busy_wait(1))) {
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k_panic();
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}
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/* Switch to requested clock */
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ADSP_CLKCTL = (ADSP_CLKCTL & ~ADSP_CLKCTL_OSC_SOURCE_MASK) |
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enc;
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/* Release other clocks */
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ADSP_CLKCTL &= ~ADSP_CLKCTL_OSC_REQUEST_MASK | enc;
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#endif
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}
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int adsp_clock_set_cpu_freq(uint32_t freq_idx)
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{
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k_spinlock_key_t k;
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int i;
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if (freq_idx >= ADSP_CPU_CLOCK_FREQ_LEN) {
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return -EINVAL;
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}
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k = k_spin_lock(&lock);
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select_cpu_clock_hw(freq_idx);
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unsigned int num_cpus = arch_num_cpus();
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for (i = 0; i < num_cpus; i++) {
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platform_cpu_clocks[i].current_freq = freq_idx;
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}
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k_spin_unlock(&lock, k);
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return 0;
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}
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struct adsp_cpu_clock_info *adsp_cpu_clocks_get(void)
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{
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return platform_cpu_clocks;
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}
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void adsp_clock_init(void)
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{
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uint32_t platform_lowest_freq_idx = ADSP_CPU_CLOCK_FREQ_LOWEST;
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int i;
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#ifdef ADSP_CLOCK_HAS_WOVCRO
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#ifdef CONFIG_SOC_SERIES_INTEL_ACE
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ACE_DfPMCCU.dfclkctl |= ACE_CLKCTL_WOVCRO;
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if (ACE_DfPMCCU.dfclkctl & ACE_CLKCTL_WOVCRO) {
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ACE_DfPMCCU.dfclkctl = ACE_DfPMCCU.dfclkctl & ~ACE_CLKCTL_WOVCRO;
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} else {
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platform_lowest_freq_idx = ADSP_CPU_CLOCK_FREQ_IPLL;
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}
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#else
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CAVS_SHIM.clkctl |= CAVS_CLKCTL_WOVCRO;
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if (CAVS_SHIM.clkctl & CAVS_CLKCTL_WOVCRO) {
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CAVS_SHIM.clkctl = CAVS_SHIM.clkctl & ~CAVS_CLKCTL_WOVCRO;
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} else {
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platform_lowest_freq_idx = ADSP_CPU_CLOCK_FREQ_LPRO;
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}
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#endif /* CONFIG_SOC_SERIES_INTEL_ACE */
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#endif /* ADSP_CLOCK_HAS_WOVCRO */
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unsigned int num_cpus = arch_num_cpus();
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for (i = 0; i < num_cpus; i++) {
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platform_cpu_clocks[i].default_freq = ADSP_CPU_CLOCK_FREQ_DEFAULT;
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platform_cpu_clocks[i].current_freq = ADSP_CPU_CLOCK_FREQ_DEFAULT;
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platform_cpu_clocks[i].lowest_freq = platform_lowest_freq_idx;
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}
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}
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struct adsp_clock_source_desc adsp_clk_src_info[ADSP_CLOCK_SOURCE_COUNT] = {
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#ifndef CONFIG_DAI_DMIC_HW_IOCLK
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[ADSP_CLOCK_SOURCE_XTAL_OSC] = { DT_PROP(DT_NODELABEL(sysclk), clock_frequency) },
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#else
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/* Temporarily use the values from the configuration until set xtal frequency via ipc
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* support is added.
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*/
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[ADSP_CLOCK_SOURCE_XTAL_OSC] = { CONFIG_DAI_DMIC_HW_IOCLK },
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(audioclk), okay)
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[ADSP_CLOCK_SOURCE_AUDIO_CARDINAL] = { DT_PROP(DT_NODELABEL(audioclk), clock_frequency) },
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(pllclk), okay)
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[ADSP_CLOCK_SOURCE_AUDIO_PLL_FIXED] = { DT_PROP(DT_NODELABEL(pllclk), clock_frequency) },
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#endif
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[ADSP_CLOCK_SOURCE_MLCK_INPUT] = { 0 },
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#ifdef ADSP_CLOCK_HAS_WOVCRO
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[ADSP_CLOCK_SOURCE_WOV_RING_OSC] = { DT_PROP(DT_NODELABEL(sysclk), clock_frequency) },
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#endif
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};
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bool adsp_clock_source_is_supported(int source)
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{
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if (source < 0 || source >= ADSP_CLOCK_SOURCE_COUNT) {
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return false;
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}
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return !!adsp_clk_src_info[source].frequency;
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}
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uint32_t adsp_clock_source_frequency(int source)
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{
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if (source < 0 || source >= ADSP_CLOCK_SOURCE_COUNT) {
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return 0;
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}
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return adsp_clk_src_info[source].frequency;
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}
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