96 lines
2.6 KiB
ArmAsm
96 lines
2.6 KiB
ArmAsm
/*
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* Copyright (c) 2018 Foundries.io Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <offsets.h>
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#include <toolchain.h>
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#include <soc.h>
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/* Exports */
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GTEXT(__soc_is_irq)
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GTEXT(__soc_handle_irq)
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#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
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GTEXT(__soc_save_context)
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GTEXT(__soc_restore_context)
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#endif
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/*
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* Whether we're in an IRQ is bog-standard RISC-V on this SoC:
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* yes if the top mcause bit is set, otherwise no.
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*/
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SECTION_FUNC(exception.other, __soc_is_irq)
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csrr a0, mcause
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srli a0, a0, 31
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ret
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/*
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* With a0 == irq_num, this is equivalent to:
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*
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* EVENT_UNIT->INTPTPENDCLEAR = (1U << irq_num);
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*
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* We could write this routine in C, but the assembly
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* that's calling us requires that a0 still contain irq_num
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* on return, and assuming nobody would ever change a
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* C implementation in a way that silently clobbers it
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* is playing with fire. Instead, we play tricks in
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* soc_context.h so that offsets.h contains a pointer to
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* INTPTPENDCLEAR.
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*/
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SECTION_FUNC(exception.other, __soc_handle_irq)
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la t0, __EVENT_INTPTPENDCLEAR
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li t1, 1
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sll t1, t1, a0
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sw t1, 0x00(t0)
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ret
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#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
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/*
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* The RI5CY core has ISA extensions for faster loop performance
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* that use extra registers.
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*
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* If the toolchain generates instructions that use them, they must be saved
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* prior to handling an interrupt/exception. This case is handled using
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* Zephyr's generic RISC-V mechanism for soc-specific context.
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*
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* For details, see the Kconfig help for CONFIG_RISCV_SOC_CONTEXT_SAVE.
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*/
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SECTION_FUNC(exception.other, __soc_save_context)
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#ifdef CONFIG_SOC_OPENISA_RV32M1_RI5CY
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csrr t0, RI5CY_LPSTART0
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csrr t1, RI5CY_LPEND0
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csrr t2, RI5CY_LPCOUNT0
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sw t0, __soc_esf_t_lpstart0_OFFSET(a0)
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sw t1, __soc_esf_t_lpend0_OFFSET(a0)
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sw t2, __soc_esf_t_lpcount0_OFFSET(a0)
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csrr t0, RI5CY_LPSTART1
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csrr t1, RI5CY_LPEND1
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csrr t2, RI5CY_LPCOUNT1
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sw t0, __soc_esf_t_lpstart1_OFFSET(a0)
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sw t1, __soc_esf_t_lpend1_OFFSET(a0)
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sw t2, __soc_esf_t_lpcount1_OFFSET(a0)
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#endif /* CONFIG_SOC_OPENISA_RV32M1_RI5CY */
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ret
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SECTION_FUNC(exception.other, __soc_restore_context)
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#ifdef CONFIG_SOC_OPENISA_RV32M1_RI5CY
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lw t0, __soc_esf_t_lpstart0_OFFSET(a0)
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lw t1, __soc_esf_t_lpend0_OFFSET(a0)
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lw t2, __soc_esf_t_lpcount0_OFFSET(a0)
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csrw RI5CY_LPSTART0, t0
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csrw RI5CY_LPEND0, t1
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csrw RI5CY_LPCOUNT0, t2
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lw t0, __soc_esf_t_lpstart1_OFFSET(a0)
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lw t1, __soc_esf_t_lpend1_OFFSET(a0)
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lw t2, __soc_esf_t_lpcount1_OFFSET(a0)
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csrw RI5CY_LPSTART1, t0
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csrw RI5CY_LPEND1, t1
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csrw RI5CY_LPCOUNT1, t2
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#endif /* CONFIG_SOC_OPENISA_RV32M1_RI5CY */
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ret
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#endif /* CONFIG_RISCV_SOC_CONTEXT_SAVE */
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