73 lines
3.5 KiB
C
73 lines
3.5 KiB
C
/* SPDX-License-Identifier: Apache-2.0 */
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/* SoC level DTS fixup file */
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#define DT_UART_QMSI_0_BAUDRATE DT_INTEL_QMSI_UART_B0002000_CURRENT_SPEED
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#define DT_UART_QMSI_0_NAME DT_INTEL_QMSI_UART_B0002000_LABEL
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#define DT_UART_QMSI_0_IRQ DT_INTEL_QMSI_UART_B0002000_IRQ_0
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#define DT_UART_QMSI_0_IRQ_PRI DT_INTEL_QMSI_UART_B0002000_IRQ_0_PRIORITY
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#define DT_UART_QMSI_0_IRQ_FLAGS DT_INTEL_QMSI_UART_B0002000_IRQ_0_SENSE
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#define DT_UART_QMSI_1_BAUDRATE DT_INTEL_QMSI_UART_B0002400_CURRENT_SPEED
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#define DT_UART_QMSI_1_NAME DT_INTEL_QMSI_UART_B0002400_LABEL
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#define DT_UART_QMSI_1_IRQ DT_INTEL_QMSI_UART_B0002400_IRQ_0
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#define DT_UART_QMSI_1_IRQ_PRI DT_INTEL_QMSI_UART_B0002400_IRQ_0_PRIORITY
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#define DT_UART_QMSI_1_IRQ_FLAGS DT_INTEL_QMSI_UART_B0002400_IRQ_0_SENSE
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#define DT_PHYS_RAM_ADDR CONFIG_SRAM_BASE_ADDRESS
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#define DT_PHYS_LOAD_ADDR CONFIG_FLASH_BASE_ADDRESS
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#define DT_RAM_SIZE CONFIG_SRAM_SIZE
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#define DT_ROM_SIZE CONFIG_FLASH_SIZE
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#define DT_IOAPIC_BASE_ADDRESS DT_INTEL_IOAPIC_FEC00000_BASE_ADDRESS
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#define CONFIG_I2C_0_NAME DT_INTEL_QMSI_I2C_B0002800_LABEL
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#define DT_I2C_0_BITRATE DT_INTEL_QMSI_I2C_B0002800_CLOCK_FREQUENCY
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#define DT_I2C_0_IRQ DT_INTEL_QMSI_I2C_B0002800_IRQ_0
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#define DT_I2C_0_IRQ_PRI DT_INTEL_QMSI_I2C_B0002800_IRQ_0_PRIORITY
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#define DT_I2C_0_IRQ_FLAGS DT_INTEL_QMSI_I2C_B0002800_IRQ_0_SENSE
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#define CONFIG_I2C_1_NAME DT_INTEL_QMSI_I2C_B0002C00_LABEL
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#define DT_I2C_1_BITRATE DT_INTEL_QMSI_I2C_B0002C00_CLOCK_FREQUENCY
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#define DT_I2C_1_IRQ DT_INTEL_QMSI_I2C_B0002C00_IRQ_0
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#define DT_I2C_1_IRQ_PRI DT_INTEL_QMSI_I2C_B0002C00_IRQ_0_PRIORITY
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#define DT_I2C_1_IRQ_FLAGS DT_INTEL_QMSI_I2C_B0002C00_IRQ_0_SENSE
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#define DT_GPIO_QMSI_0_NAME DT_INTEL_QMSI_GPIO_B0000C00_LABEL
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#define DT_GPIO_QMSI_0_IRQ DT_INTEL_QMSI_GPIO_B0000C00_IRQ_0
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#define DT_GPIO_QMSI_0_IRQ_PRI DT_INTEL_QMSI_GPIO_B0000C00_IRQ_0_PRIORITY
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#define DT_GPIO_QMSI_0_IRQ_FLAGS DT_INTEL_QMSI_GPIO_B0000C00_IRQ_0_SENSE
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#define DT_GPIO_QMSI_1_NAME DT_INTEL_QMSI_GPIO_B0800B00_LABEL
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#define DT_GPIO_QMSI_1_IRQ DT_INTEL_QMSI_GPIO_B0800B00_IRQ_0
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#define DT_GPIO_QMSI_1_IRQ_PRI DT_INTEL_QMSI_GPIO_B0800B00_IRQ_0_PRIORITY
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#define DT_GPIO_QMSI_1_IRQ_FLAGS DT_INTEL_QMSI_GPIO_B0800B00_IRQ_0_SENSE
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#define DT_RTC_0_NAME DT_INTEL_QMSI_RTC_B0000400_LABEL
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#define DT_RTC_0_IRQ DT_INTEL_QMSI_RTC_B0000400_IRQ_0
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#define DT_RTC_0_IRQ_PRI DT_INTEL_QMSI_RTC_B0000400_IRQ_0_PRIORITY
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#define DT_RTC_0_IRQ_FLAGS DT_INTEL_QMSI_RTC_B0000400_IRQ_0_SENSE
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#define DT_SPI_0_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_B0001000_BASE_ADDRESS
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#define DT_SPI_0_NAME DT_SNPS_DESIGNWARE_SPI_B0001000_LABEL
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#define DT_SPI_0_IRQ DT_SNPS_DESIGNWARE_SPI_B0001000_IRQ_0
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#define DT_SPI_0_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_B0001000_IRQ_0_PRIORITY
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#define DT_SPI_1_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_B0001400_BASE_ADDRESS
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#define DT_SPI_1_NAME DT_SNPS_DESIGNWARE_SPI_B0001400_LABEL
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#define DT_SPI_1_IRQ DT_SNPS_DESIGNWARE_SPI_B0001400_IRQ_0
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#define DT_SPI_1_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_B0001400_IRQ_0_PRIORITY
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#define DT_SPI_2_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_B0001800_BASE_ADDRESS
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#define DT_SPI_2_NAME DT_SNPS_DESIGNWARE_SPI_B0001800_LABEL
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#define DT_SPI_2_IRQ DT_SNPS_DESIGNWARE_SPI_B0001800_IRQ_0
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#define DT_SPI_2_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_B0001800_IRQ_0_PRIORITY
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#define CONFIG_WDT_0_NAME DT_INTEL_QMSI_WATCHDOG_B0000000_LABEL
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#define DT_WDT_0_IRQ DT_INTEL_QMSI_WATCHDOG_B0000000_IRQ_0
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#define DT_WDT_0_IRQ_PRI DT_INTEL_QMSI_WATCHDOG_B0000000_IRQ_0_PRIORITY
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#define DT_WDT_0_IRQ_FLAGS DT_INTEL_QMSI_WATCHDOG_B0000000_IRQ_0_SENSE
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/* End of SoC Level DTS fixup file */
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