148 lines
4.0 KiB
Plaintext
148 lines
4.0 KiB
Plaintext
# Kconfig - STM32F1X Connectivity Line MCU clock control driver config
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#
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# Copyright (c) 2016 RnDity Sp. z o.o.
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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if SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE
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menuconfig CLOCK_CONTROL_STM32F10X_CONN_LINE
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bool
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prompt "STM32F107x Reset & Clock Control"
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default y if SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE
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help
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Enable driver for Reset & Clock Control subsystem found
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in STM32F105/STM32F107 family of MCUs
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config CLOCK_CONTROL_STM32F10X_CONN_LINE_DEVICE_INIT_PRIORITY
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int "Clock Control Device Priority"
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default 1
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depends on CLOCK_CONTROL_STM32F10X_CONN_LINE
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help
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This option controls the priority of clock control
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device initialization. Higher priority ensures that the device
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is initialized earlier in the startup cycle. If unsure, leave
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at default value 1
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choice
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prompt "STM32F10x Connectivity Line System Clock Source"
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depends on CLOCK_CONTROL_STM32F10X_CONN_LINE
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config CLOCK_STM32F10X_CONN_LINE_SYSCLK_SRC_HSI
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bool "HSI"
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help
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Use HSI as source of SYSCLK
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config CLOCK_STM32F10X_CONN_LINE_SYSCLK_SRC_HSE
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bool "HSE"
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help
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Use HSE as source of SYSCLK
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config CLOCK_STM32F10X_CONN_LINE_SYSCLK_SRC_PLLCLK
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bool "PLLCLK"
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help
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Use PLLCLK as source of SYSCLK
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endchoice
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choice
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prompt "STM32F10x Connectivity Line PLL Clock Source"
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depends on CLOCK_CONTROL_STM32F10X_CONN_LINE && CLOCK_STM32F10X_CONN_LINE_SYSCLK_SRC_PLLCLK
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config CLOCK_STM32F10X_CONN_LINE_PLL_SRC_HSI
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bool "HSI"
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help
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Use HSI divided by 2 as source of PLL
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config CLOCK_STM32F10X_CONN_LINE_PLL_SRC_PREDIV1
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bool "PREDIV1"
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help
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Use clock from PREDIV1 as source of PLL
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endchoice
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choice
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prompt "STM32F10x Connectivity Line PREDIV1 entry clock source"
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depends on CLOCK_CONTROL_STM32F10X_CONN_LINE && CLOCK_STM32F10X_CONN_LINE_PLL_SRC_PREDIV1
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config CLOCK_STM32F10X_CONN_LINE_PREDIV1_SRC_HSE
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bool "HSE"
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help
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Use HSE as source of PREDIV1
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config CLOCK_STM32F10X_CONN_LINE_PREDIV1_SRC_PLL2CLK
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bool "PLL2CLK"
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help
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Use clock from PLL2CLK as source of PLL
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endchoice
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config CLOCK_STM32F10X_CONN_LINE_HSE_BYPASS
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bool "HSE bypass"
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depends on CLOCK_CONTROL_STM32F10X_CONN_LINE && (CLOCK_STM32F10X_CONN_LINE_SYSCLK_SRC_HSE || CLOCK_STM32F10X_CONN_LINE_PREDIV1_SRC_HSE)
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help
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Enable this option to bypass external high-speed clock (HSE).
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config CLOCK_STM32F10X_CONN_LINE_PREDIV1
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int "PREDIV1 Prescaler"
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depends on CLOCK_CONTROL_STM32F10X_CONN_LINE && CLOCK_STM32F10X_CONN_LINE_PLL_SRC_PREDIV1
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default 0
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range 0 16
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help
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PREDIV1 is PREDIV1SCR clock signal prescaler, allowed values: 0 - 16.
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config CLOCK_STM32F10X_CONN_LINE_PLL_MULTIPLIER
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int "PLL multiplier"
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depends on CLOCK_CONTROL_STM32F10X_CONN_LINE && CLOCK_STM32F10X_CONN_LINE_SYSCLK_SRC_PLLCLK
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default 9
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range 4 13
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help
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PLL multiplier, allowed values: 4 - 9 and 13 (in fact the multiplication factor is 6.5).
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Values in range 10-12 are reserved. PLL output must not exceed 72MHz.
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config CLOCK_STM32F10X_CONN_LINE_PLL2_MULTIPLIER
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int "PLL2 multiplier"
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depends on CLOCK_CONTROL_STM32F10X_CONN_LINE && CLOCK_STM32F10X_CONN_LINE_PREDIV1_SRC_PLL2CLK
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default 8
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range 8 20
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help
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PLL2 multiplier, allowed values: 8 - 20. PLL2 output must not exceed 72MHz.
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config CLOCK_STM32F10X_CONN_LINE_PREDIV2
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int "PREDIV2 Prescaler"
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depends on CLOCK_CONTROL_STM32F10X_CONN_LINE && CLOCK_STM32F10X_CONN_LINE_PREDIV1_SRC_PLL2CLK
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default 0
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range 0 16
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help
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PREDIV2 is HSE prescaler, allowed values: 0 - 16.
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config CLOCK_STM32F10X_CONN_LINE_AHB_PRESCALER
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int "AHB prescaler"
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depends on CLOCK_CONTROL_STM32F10X_CONN_LINE
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default 0
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range 0 512
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help
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AHB prescaler, allowed values: 0, 2, 4, 8, 16, 64, 128,
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256, 512.
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config CLOCK_STM32F10X_CONN_LINE_APB1_PRESCALER
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int "APB1 prescaler"
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depends on CLOCK_CONTROL_STM32F10X_CONN_LINE
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default 0
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range 0 16
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help
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APB1 Low speed clock (PCLK1) prescaler, allowed values:
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0, 2, 4, 8, 16. The APB1 clock must not exceed 36MHz.
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config CLOCK_STM32F10X_CONN_LINE_APB2_PRESCALER
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int "APB2 prescaler"
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depends on CLOCK_CONTROL_STM32F10X_CONN_LINE
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default 0
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range 0 16
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help
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APB2 High speed clock (PCLK2) prescaler, allowed values:
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0, 2, 4, 8, 16
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endif
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