# Kconfig - STM32F1X Connectivity Line MCU clock control driver config
#
# Copyright (c) 2016 RnDity Sp. z o.o.
#
# SPDX-License-Identifier: Apache-2.0
#

if SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE

menuconfig CLOCK_CONTROL_STM32F10X_CONN_LINE
	bool
	prompt "STM32F107x Reset & Clock Control"
	default y if SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE
	help
	 Enable driver for Reset & Clock Control subsystem found
	 in STM32F105/STM32F107 family of MCUs

config CLOCK_CONTROL_STM32F10X_CONN_LINE_DEVICE_INIT_PRIORITY
	int "Clock Control Device Priority"
	default 1
	depends on CLOCK_CONTROL_STM32F10X_CONN_LINE
	help
	 This option controls the priority of clock control
	 device initialization. Higher priority ensures that the device
	 is initialized earlier in the startup cycle. If unsure, leave
	 at default value 1

choice
prompt "STM32F10x Connectivity Line System Clock Source"
depends on CLOCK_CONTROL_STM32F10X_CONN_LINE

config CLOCK_STM32F10X_CONN_LINE_SYSCLK_SRC_HSI
	bool "HSI"
	help
	 Use HSI as source of SYSCLK

config CLOCK_STM32F10X_CONN_LINE_SYSCLK_SRC_HSE
	bool "HSE"
	help
	 Use HSE as source of SYSCLK

config CLOCK_STM32F10X_CONN_LINE_SYSCLK_SRC_PLLCLK
	bool "PLLCLK"
	help
	 Use PLLCLK as source of SYSCLK

endchoice

choice
prompt "STM32F10x Connectivity Line PLL Clock Source"
depends on CLOCK_CONTROL_STM32F10X_CONN_LINE && CLOCK_STM32F10X_CONN_LINE_SYSCLK_SRC_PLLCLK

config CLOCK_STM32F10X_CONN_LINE_PLL_SRC_HSI
	bool "HSI"
	help
	 Use HSI divided by 2 as source of PLL

config CLOCK_STM32F10X_CONN_LINE_PLL_SRC_PREDIV1
	bool "PREDIV1"
	help
	 Use clock from PREDIV1 as source of PLL

endchoice

choice
prompt "STM32F10x Connectivity Line PREDIV1 entry clock source"
depends on CLOCK_CONTROL_STM32F10X_CONN_LINE && CLOCK_STM32F10X_CONN_LINE_PLL_SRC_PREDIV1

config CLOCK_STM32F10X_CONN_LINE_PREDIV1_SRC_HSE
	bool "HSE"
	help
	 Use HSE as source of PREDIV1

config CLOCK_STM32F10X_CONN_LINE_PREDIV1_SRC_PLL2CLK
	bool "PLL2CLK"
	help
	 Use clock from PLL2CLK as source of PLL

endchoice

config CLOCK_STM32F10X_CONN_LINE_HSE_BYPASS
	bool "HSE bypass"
	depends on CLOCK_CONTROL_STM32F10X_CONN_LINE && (CLOCK_STM32F10X_CONN_LINE_SYSCLK_SRC_HSE || CLOCK_STM32F10X_CONN_LINE_PREDIV1_SRC_HSE)
	help
	 Enable this option to bypass external high-speed clock (HSE).

config CLOCK_STM32F10X_CONN_LINE_PREDIV1
	int "PREDIV1 Prescaler"
	depends on CLOCK_CONTROL_STM32F10X_CONN_LINE && CLOCK_STM32F10X_CONN_LINE_PLL_SRC_PREDIV1
	default 0
	range 0 16
	help
	 PREDIV1 is PREDIV1SCR clock signal prescaler, allowed values: 0 - 16.

config CLOCK_STM32F10X_CONN_LINE_PLL_MULTIPLIER
	int "PLL multiplier"
	depends on CLOCK_CONTROL_STM32F10X_CONN_LINE && CLOCK_STM32F10X_CONN_LINE_SYSCLK_SRC_PLLCLK
	default 9
	range 4 13
	help
	 PLL multiplier, allowed values: 4 - 9 and 13 (in fact the multiplication factor is 6.5).
	 Values in range 10-12 are reserved. PLL output must not exceed 72MHz.

config CLOCK_STM32F10X_CONN_LINE_PLL2_MULTIPLIER
	int "PLL2 multiplier"
	depends on CLOCK_CONTROL_STM32F10X_CONN_LINE && CLOCK_STM32F10X_CONN_LINE_PREDIV1_SRC_PLL2CLK
	default 8
	range 8 20
	help
	 PLL2 multiplier, allowed values: 8 - 20. PLL2 output must not exceed 72MHz.

config CLOCK_STM32F10X_CONN_LINE_PREDIV2
	int "PREDIV2 Prescaler"
	depends on CLOCK_CONTROL_STM32F10X_CONN_LINE && CLOCK_STM32F10X_CONN_LINE_PREDIV1_SRC_PLL2CLK
	default 0
	range 0 16
	help
	 PREDIV2 is HSE prescaler, allowed values: 0 - 16.

config CLOCK_STM32F10X_CONN_LINE_AHB_PRESCALER
	int "AHB prescaler"
	depends on CLOCK_CONTROL_STM32F10X_CONN_LINE
	default 0
	range 0 512
	help
	 AHB prescaler, allowed values: 0, 2, 4, 8, 16, 64, 128,
	 256, 512.

config CLOCK_STM32F10X_CONN_LINE_APB1_PRESCALER
	int "APB1 prescaler"
	depends on CLOCK_CONTROL_STM32F10X_CONN_LINE
	default 0
	range 0 16
	help
	 APB1 Low speed clock (PCLK1) prescaler, allowed values:
	 0, 2, 4, 8, 16. The APB1 clock must not exceed 36MHz.

config CLOCK_STM32F10X_CONN_LINE_APB2_PRESCALER
	int "APB2 prescaler"
	depends on CLOCK_CONTROL_STM32F10X_CONN_LINE
	default 0
	range 0 16
	help
	 APB2 High speed clock (PCLK2) prescaler, allowed values:
	 0, 2, 4, 8, 16

endif