31 lines
1.3 KiB
Plaintext
31 lines
1.3 KiB
Plaintext
/* SoC level DTS fixup file */
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#define CONFIG_UART_NS16550_PORT_0_BASE_ADDR NS16550_000003F8_BASE_ADDRESS
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#define CONFIG_UART_NS16550_PORT_0_BAUD_RATE NS16550_000003F8_CURRENT_SPEED
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#define CONFIG_UART_NS16550_PORT_0_NAME NS16550_000003F8_LABEL
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#define CONFIG_UART_NS16550_PORT_0_IRQ NS16550_000003F8_IRQ_0
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#define CONFIG_UART_NS16550_PORT_0_IRQ_PRI NS16550_000003F8_IRQ_0_PRIORITY
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#define CONFIG_UART_NS16550_PORT_0_IRQ_FLAGS NS16550_000003F8_IRQ_0_SENSE
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#define CONFIG_UART_NS16550_PORT_0_CLK_FREQ NS16550_000003F8_CLOCK_FREQUENCY
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#define CONFIG_UART_NS16550_PORT_1_BASE_ADDR NS16550_000002F8_BASE_ADDRESS
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#define CONFIG_UART_NS16550_PORT_1_BAUD_RATE NS16550_000002F8_CURRENT_SPEED
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#define CONFIG_UART_NS16550_PORT_1_NAME NS16550_000002F8_LABEL
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#define CONFIG_UART_NS16550_PORT_1_IRQ NS16550_000002F8_IRQ_0
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#define CONFIG_UART_NS16550_PORT_1_IRQ_PRI NS16550_000002F8_IRQ_0_PRIORITY
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#define CONFIG_UART_NS16550_PORT_1_IRQ_FLAGS NS16550_000002F8_IRQ_0_SENSE
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#define CONFIG_UART_NS16550_PORT_1_CLK_FREQ NS16550_000002F8_CLOCK_FREQUENCY
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#define CONFIG_PHYS_RAM_ADDR CONFIG_SRAM_BASE_ADDRESS
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#define CONFIG_PHYS_LOAD_ADDR CONFIG_FLASH_BASE_ADDRESS
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#define CONFIG_RAM_SIZE CONFIG_SRAM_SIZE
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#define CONFIG_ROM_SIZE CONFIG_FLASH_SIZE
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#define CONFIG_IOAPIC_BASE_ADDRESS INTEL_IOAPIC_FEC00000_BASE_ADDRESS
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/* End of SoC Level DTS fixup file */
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