zephyr/arch/x86/soc/ia32/dts.fixup

/* SoC level DTS fixup file */

#define CONFIG_UART_NS16550_PORT_0_BASE_ADDR	NS16550_000003F8_BASE_ADDRESS
#define CONFIG_UART_NS16550_PORT_0_BAUD_RATE	NS16550_000003F8_CURRENT_SPEED
#define CONFIG_UART_NS16550_PORT_0_NAME		NS16550_000003F8_LABEL
#define CONFIG_UART_NS16550_PORT_0_IRQ		NS16550_000003F8_IRQ_0
#define CONFIG_UART_NS16550_PORT_0_IRQ_PRI	NS16550_000003F8_IRQ_0_PRIORITY
#define CONFIG_UART_NS16550_PORT_0_IRQ_FLAGS	NS16550_000003F8_IRQ_0_SENSE
#define CONFIG_UART_NS16550_PORT_0_CLK_FREQ	NS16550_000003F8_CLOCK_FREQUENCY

#define CONFIG_UART_NS16550_PORT_1_BASE_ADDR	NS16550_000002F8_BASE_ADDRESS
#define CONFIG_UART_NS16550_PORT_1_BAUD_RATE	NS16550_000002F8_CURRENT_SPEED
#define CONFIG_UART_NS16550_PORT_1_NAME		NS16550_000002F8_LABEL
#define CONFIG_UART_NS16550_PORT_1_IRQ		NS16550_000002F8_IRQ_0
#define CONFIG_UART_NS16550_PORT_1_IRQ_PRI	NS16550_000002F8_IRQ_0_PRIORITY
#define CONFIG_UART_NS16550_PORT_1_IRQ_FLAGS	NS16550_000002F8_IRQ_0_SENSE
#define CONFIG_UART_NS16550_PORT_1_CLK_FREQ	NS16550_000002F8_CLOCK_FREQUENCY

#define CONFIG_PHYS_RAM_ADDR			CONFIG_SRAM_BASE_ADDRESS

#define CONFIG_PHYS_LOAD_ADDR			CONFIG_FLASH_BASE_ADDRESS

#define CONFIG_RAM_SIZE				CONFIG_SRAM_SIZE

#define CONFIG_ROM_SIZE				CONFIG_FLASH_SIZE


#define CONFIG_IOAPIC_BASE_ADDRESS		INTEL_IOAPIC_FEC00000_BASE_ADDRESS

/* End of SoC Level DTS fixup file */